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this document contains complete and detai led description of all modules included in the avr xmega tm a microcontroller family. the xmega a is a family of low power, high performance and peripheral rich cmos 8/16-bit microcontrollers based on the avr? enhanced risc architecture. the available xmega a modules described in this manual are: ? avr cpu ? memories ? dmac - direct memory access controller ? event system ? system clock and clock options ? power management and sleep modes ? system contrl and reset ? wdt - watchdog timer ? interrupts and programmable multi-level interrupt controller ? i/o ports ? tc - 16-bit timer/counter ? awex - advanced waveform extension ? hi-res - high reso lution extension ? rtc - real time counter ? twi - two wire serial interface ? spi - serial programmable interface ? usart - universal synchronous and asynchro nous serial receiver and transmitter ? ircom - ir communication module ? crypto engines ? ebi - external bus interface ? adc - analog to digital converter ? dac - digital to analog converter ? ac - analog comparator ? ieee 1149.1 jtag bounda ry scan interface ? pdi - program and debug interface ? memory programming ? instruction set summary 8077b- avr-06/08 8-bit xmega a microcontroller xmega a manual preliminary
2 8077b?avr?06/08 xmega a 1. about this manual this document contains in-depth documentation of all peripherals and modules available for the avr xmega a microcontroller family. all feat ures are documented on a functional level and described in a general sense. all peripherals a nd modules described in this manual may not be present in all xmega a devices. all device specific information such as characterization data, memory sizes, modules and peripherals available and their absolute memory addresses refer to the device datasheets. when several instances of one peripheral such as a port exist in one device, each instance of a module will have a unique name, such as porta, portb etc. register, bit names are unique within one module. for more details on applied use and code examples for all peripherals and modules, refer to the xmega a specific applicat ion notes available from : http://www.atmel.com/avr. 1.1 reading the manual the main sections in the manual describes the various modules. they contain a short feature list of the most important features and a short overview describing the module. the remaining sec- tion describes the features and functions in more details. the register description sections lists all r egisters, and describe each bit/flag and its function. this includes details on how to set up and enable various features in the module. when multiple bits are needed for a configuration setting, these are grouped together in a bit group. the possi- ble bit group configurations are listed for all bit groups together with their associated group configuration and a short description. the group configuration refer to the defined configuration name used in the xmega c and assembler header files and application note source code. the register summary sections lists the internal register map for each module type. the interrupt vector summary sections list the interrupt vectors and offset address for each mod- ule type. 1.2 resources a comprehensive set of development tools, app lication notes and datasheets are available for download on http:// www.atmel.com/avr. 1.3 recommended reading ? xmega a device datasheets ? xmega a application notes this device data sheet only contains general modules and peripheral descriptions. the xmega a device datasheet contains device specific information. the xmega a application notes con- tain example code and show applied use of the modules and peripherals. before starting the first development it is especially recommended to read the avr1000 - get- ting started writing c-code for xmega, and avr1900 - getting started with atxmega128a1 application notes.
3 8077b?avr?06/08 xmega a 2. overview the xmega a is a family of low power, high performance and peripheral rich cmos 8/16-bit microcontrollers based on the avr? enhanced risc architecture. by executing powerful instructions in a single clo ck cycle, the xmega a achieves throughputs approaching 1 million instructions per second (mips) per mhz allowing the system desi gner to optimi ze power con- sumption versus processing speed. the avr cpu combines a rich instruction set with 32 general purpose working registers. all the 32 registers are directly connected to the arithmetic logic unit (alu), allowing two independent registers to be accessed in one single instructi on, executed in one clock cycle. the resulting architecture is more code efficient while achi eving throughputs many times faster than conven- tional single-accumula tor or cisc based microcontrollers. the xmega a devices provide the following features: in-system programmable flash with read-while-write capabilities, internal eep rom and sram, four-channel dma controller, eight-channel event system and programmable multi-level interrupt controller, up to 78 general purpose i/o lines, 16-bit real time counter (rtc), up to eight flexible 16-bit timer/counters with compare modes and pwm, up to eight usarts, up to four two wire serial interfaces (twis), up to four serial peri pheral interfaces (spis), aes and des crypto engine, up to two 8- channel, 12-bit adcs with optional differential input with programmable gain, up to two 2-chan- nel, 12-bit dacs, up to four analog comparators with window mode, programmable watchdog timer with separate internal os cillator, accurate internal os cillators with pll and prescaler and programmable brown-out detection. the program and debug interface (pdi), a fast 2-pin interface for programming and debugging, is available. the devices also have an ieee std. 1149.1 compliant jtag test interface, and this can also be used for on-chip debug and programming. the xmega a devices have five software selectable po wer saving modes. th e idle mode stops the cpu while allowing the sram, dma controll er, event system, interrupt controller and all peripherals to continue functioning. the power-down mode saves the sram and register con- tents but stops the oscillators, disabling all other functions until the next twi or pin-change interrupt, or reset. in power-save mode, the asynchronous real time counter continues to run, allowing the application to maintain a timer base while the rest of the device is sleeping. in standby mode, the crystal/resonator oscillator is kept running while the rest of the device is sleeping. this allows very fast start-up from external crystal combined with low power consump- tion. in extended standby mode, both the main oscillator and the asynchronous timer continue to run. to further reduce power consumption, the peripheral clock to each individual peripheral can optionally be stopped in active mode and idle sleep mode. the devices are manufactured using atmel's high-density nonvolatile memory technology. the program flash memory can be reprogrammed in-system through the pdi or jtag. a bootloader running in the device can use any interface to download the application program to the flash memory. the bootloader software in the boot flash section will continue to run while the appli- cation flash section is updated, providing true read-while-write operation. by combining an 8/16-bit risc cpu with in-syste m self-programmable flash, th e atmel xmega a is a powerful microcontroller family that provides a highly flexible and cost effective solution for many embed- ded applications. the xmega a devices are supported with a full suite of program and system development tools including: c compilers, macro assemblers, program debugger/simulators, programmers, and evaluation kits.
4 8077b?avr?06/08 xmega a 2.1 block diagram figure 2-1. xmega a block diagram 2.2 recommended reading ? xmega device data sheet ? application notes power supervision por/bod & reset port a (8) port b (8) event routing network event routing network dma controller bus controller sram ebi adca daca aca dacb adcb acb ocd internal reference port k (8) port j (8) port h (8) pdi cpu ph[0..7] pj[0..7] pk[0..7] pa[0..7] pb[0..7]/ jtag watchdog timer watchdog oscillator interrupt controller data bus data bus prog/debug controller vcc gnd port r (2) xtal1 xtal2 pr[0..1] tosc1 tosc2 pq[0..7] oscillator circuits/ clock generation oscillator control real time counter event system controller jtag arefa arefb pdi_d reset/ pdi_clk port b sleep controller flash eeprom nvm controller des aes ircom port c (8) pc[0..7] tcc0:1 usartc0:1 twic spic port d (8) pd[0..7] tcd0:1 usartd0:1 twid spid port e (8) pe[0..7] tce0:1 usarte0:1 twie spie port f (8) pf[0..7] tcf0:1 usartf0:1 twif spif port g (8) pg[0..7] port l (8) pl[0..7] port q (8) port n (8) port p (8) port m (8) pl[0..7] pp[0..7] pn[0..7]
5 8077b?avr?06/08 xmega a 3. avr cpu 3.1 features ? 8/16-bit high perfor mance avr risc cpu ? 138 instructions ? hardware multiplier ? 32x8-bit registers directly connected to the alu ? stack in ram ? stack pointer accessible in i/o memory space ? direct addressing of up to 16m bytes of program and data memory ? true 16/24-bit access to 16/24-bit i/o registers ? efficient support for both 8-, 16- and 32-bit arithmetic ? configuration change protection of system critical features 3.2 overview xmega uses the 8/16-bit avr cpu. the main function of the cpu is to ensure correct program execution. the cpu is able to access memories, perform calculations and control peripherals. interrupt handling is described in a separate section, refer to ?interrupts and programmable multi-level inte rrupt controller? on page 108 for more details on this. 3.3 architectural overview in order to maximize performance and parallelism, the avr uses a harvard architecture with separate memories and buses for program and data. instructions in the program memory are executed with a single level pipelining. while one instruction is being executed, the next instruc- tion is pre-fetched from the program memory. this concept enables instructions to be executed in every clock cycle. for detailed description of all instructions refer to the instruction set appendix.
6 8077b?avr?06/08 xmega a figure 3-1. block diagram of the avr architecture the arithmetic logic unit (alu) supports arit hmetic and logic operations between registers or between a constant and a register. single register operations can also be executed in the alu. after an arithmetic operation, the status register is updated to reflect information about the result of the operation. the alu is directly connected to the fast-access register file. the 32 x 8-bit general purpose working registers all have single clock cycle access time allowing single-cycle arithmetic logic unit (alu) operation between registers or between a register and an immediate. six of the 32 registers can be used as three 16-bit address po inters for program and data space addressing - enabling efficient address calculations. the memory spaces are all linear and regular memory maps. the data memory space and the program memory space are two different memory spaces. the data memory space is divi ded into i/o registers and sr am. in addition the eeprom can be memory mapped in the data memory. all i/o status and control registers reside in the lowest 4k bytes addresses of the data memory. this is referred to as the i/o memory space. th e lowest 64 addresses ca n be accessed directly, or as the data space locations from 0x00 - 0x 3f. the rest is the extended i/o memory space, ranging from 0x40 to 0x1fff. i/o registers here must be access as data space locations using load (ld/lds/ldd) and store (st/sts/std) instructions. flash program memory instruction decode program counter ocd 32 x 8 general purpose registers alu multiplier/ des instruction register status/ control peripheral module 1 peripheral module n eeprom pmic sram data bus data bus
7 8077b?avr?06/08 xmega a the sram holds data, and code cannot be exec uted from here. it can easily be accessed through the five different addressing modes s upported in the avr architecture. the first sram address is 0x2000. data address 0x1000 to 0x1fff is reserved for me mory mapping of eeprom. the program memory is divided in two sections , the application program section and the boot program section. both sections have dedicated lock bits for write and read/write protection. the spm instruction that is used for self-programming of the application flash memory must reside in the boot program section. a third section exists inside the application section. this section, the application table section, has separate lock bits for write and read/write protection. the application table section can be used for storing non-volatile data or application software. 3.4 alu - arithmetic logic unit the arithmetic logic unit (alu) supports arit hmetic and logic operations between registers or between a constant and a register. single regist er operations can also be executed. the alu operates in direct connection with all the 32 general purpose registers. in a typical single cycle alu operation, two operands are output from the register file, the operation is executed, and the result is stored back in the register file. in order to operate on data in the data memory, these must first be loaded into the register file. after the operation, the data can be stored from the register file and back to the data memory. the alu operations are divided into three main categories - arithmetic, logical, and bit-functions. after an arithmetic or logic operation, the status register is updated to reflect information about the result of the operation. 3.4.1 hardware multiplier the multiplier is capable of multiplying two 8-bit numbers into a 16-bit result. the hardware mul- tiplier supports different variations of signed and unsigned integer and fractional numbers: ? multiplication of unsigned integers. ? multiplication of signed integers. ? multiplication of a signed integer with an unsigned integer. ? multiplication of unsigned fractional numbers. ? multiplication of signed fractional numbers. ? multiplication of a signed fractional number and with an unsigned. a multiplication takes two cpu clock cycles. 3.5 program flow after reset, the program will start to execute from prog ram address 0. progra m flow is provided by conditional and unconditional jump and call instru ctions, able to directly address the whole address space. most instructions have a single 16-bit word format. every program memory address contains a 16- or 32-bit instruction. the program counter (pc) addresses the location from where instructions are fetched. during inte rrupts and subroutine calls, the return address pc is stored on the stack.
8 8077b?avr?06/08 xmega a when an enabled interrupt occurs, the program counter is vectored to the actual interrupt vector in order to execute the interrupt handling routine. hardware clears the corresponding interrupt flag automatically. a flexible interrupt controller has dedicated control registers with an additional global interrupt enable bit in the status register. all interrupts have a separate interrupt vector, starting from the reset vector at address 0 in the program memory. all interrupts have a programmable interrupt level. within each level they ha ve priority in accordance with their interrupt vector position where the lower interrupt vector address has the higher priority. 3.6 instruction execution timing the avr cpu is driven by the cpu clock clk cpu . no internal clock division is used. figure 3-2 on page 8 shows the parallel instruction fetches and instruction executions enabled by the har- vard architecture and the fast-access register file concept. this is the basic pipelining concept to obtain up to 1 mips per mhz with the corr esponding unique results for functions per cost, functions per clocks, and functions per power-unit. figure 3-2. the parallel instruction fetches and instruction executions figure 3-3 on page 8 shows the internal timing concept for the register file. in a single clock cycle an alu operation using two register operands is executed, and the result is stored back to the destination register. figure 3-3. single cycle alu operation clk 1st instruction fetch 1st instruction execute 2nd instruction fetch 2nd instruction execute 3rd instruction fetch 3rd instruction execute 4th instruction fetch t1 t2 t3 t4 cpu total execution time register operands fetch alu operation execute result write back t1 t2 t3 t4 clk cpu
9 8077b?avr?06/08 xmega a 3.7 status register the status register (sreg) contains information about the result of the most recently executed arithmetic or logic instruction. this information can be used for altering program flow in order to perform conditional operations. note that the st atus register is updated after all alu opera- tions, as specified in the instruction set referenc e. this will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. the status register is not automatically stored when entering an interrupt routine nor restored when returning from an interrupt. this must be handled by software. the status register is accessible in the i/o memory space. 3.8 stack and stack pointer the stack is used for storing return addresses after interrupts and subroutine calls. it can also be used for storing temporary data. the stack pointer (sp) register always points to the top of the stack. it is implemented as two 8-bit register s that is accessible in the i/o memory space. data is pushed and popped from the stack usi ng the push and pop instructions. the stack is implemented as growing from higher memory locations to lower memory locations. this implies that a pushing data on the stack decreases the sp, and popping data off the stack increases the sp.the sp is automatically loaded after reset, and the initial value is the highest address of the internal sram. if the sp is changed, it must be set to point above address 0x2000 and it must be defined before any subroutine calls are executed or before interrupts are enabled. during interrupts or subroutine calls the return address is automatically pushed on the stack. the return address can be two or three bytes, de pending of the memory size of the device. for devices with 128k bytes or less of program memory the return address is two bytes, hence the stack pointer is decremented/incremented by two. for devices with more than 128k bytes of program memory, the return address is three by tes, hence the sp is decremented/incremented by three. the return address is popped of the stack when returning from interrupts using the reti instruction, and subroutine calls using the ret instruction. the sp is decremented by one when data is pus hed onto the stack with the push instruction, and incremented by one when data is popped off the stack using the pop instruction. to prevent corruption when updating the stack pointer from software, a write to spl will auto- matically disable interrupts for up to 4 instructions or until the next i/o memory write. 3.9 register file the register file consists of 32 x 8-bit general purpose registers. in order to achieve the required performance and flexib ility, the register file supp orts the followin g input/output schemes: ? one 8-bit output operand and one 8-bit result input ? two 8-bit output operands and one 8-bit result input ? two 8-bit output operands and one 16-bit result input ? one 16-bit output operand and one 16-bit result input
10 8077b?avr?06/08 xmega a figure 3-4. avr cpu general purpose working registers most of the instructions operating on the register file have direct access to all registers, and most of them are single cycle instructions. the register file is located in a separate address space, so the registers are not accessible as data memory. 3.9.1 the x-, y- and z- registers the registers r26..r31 have added functions besides their general-purpose usage. these registers can form 16-bit address pointers for addressing of the data memory. the three address registers is called the x-, y-, and z-register. the z-register can also be used as an address pointer to read from and/or write to the flash program memory, signature rows, fuses and lock bits. figure 3-5. the x-, y- and z-registers the lowest register address holds the least significant byte (lsb). in the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 7 0 addr. r0 0x00 r1 0x01 r2 0x02 ? r13 0x0d general r14 0x0e purpose r15 0x0f working r16 0x10 registers r17 0x11 ? r26 0x1a x-register low byte r27 0x1b x-register high byte r28 0x1c y-register low byte r29 0x1d y-register high byte r30 0x1e z-register low byte r31 0x1f z-register high byte bit (individually) 7 r27 07 r26 0 x-register xh xl bit (x-register) 15 8 7 0 bit (individually) 7 r29 07 r28 0 y-register yh yl bit (y-register) 15 8 7 0 bit (individually) 7 r31 07 r30 0 z-register zh zl bit (z-register) 15 8 7 0
11 8077b?avr?06/08 xmega a 3.10 ramp and extended indirect registers in order to access program memory or data memory above 64k bytes, the address or address pointer must be more than 16-bits. this is done by concatenating one register to one of the x-, y- or z-registers, and this register then holds the most significant byte (msb) in a 24-bit address or address pointer. these registers are only available on devices with external bus interface and/or more than 64k bytes of program or data memory space. for these devices, only the number of bits required to address the whole program and data memory space in the device is implemented in the registers. 3.10.1 rampx, rampy and rampz registers the rampx, rampy and rampz registers are concatenated with the x-, y-, and z-registers respectively to enable indirect addressing of the whole data memory space above 64k bytes and up to 16m bytes. figure 3-6. the combined rampx + x, ram py + y and rampz + z registers when reading (elpm) and writing (spm) program memory locations above the first 128k bytes of the program memory, rampz is concatenated with the z-register to form the 24-bit address. lpm is not affected by the rampz setting. 3.10.2 rampd register this register is concatenated with the operand to enable direct addressing of the whole data memory space above 64k bytes. together ramp d and the operand will form a 24-bit address. figure 3-7. the combined rampd + k register 3.10.3 eind - extended indirect register eind is concatenated with the z-register to enable indirect jump and call to locations above the first 128k bytes (64k words) of the program memory. figure 3-8. the combined eind + z register bit (individually) 7 0 7 0 7 0 rampx xh xl bit (x-pointer) 23 16 15 8 7 0 bit (individually) 7 0 7 0 7 0 rampy yh yl bit (y-pointer) 23 16 15 8 7 0 bit (individually) 7 0 7 0 7 0 rampz zh zl bit (z-pointer) 23 16 15 8 7 0 bit (individually) 7 0 15 0 rampd k bit (d-pointer) 23 16 15 0 bit (individually) 7 0 7 0 7 0 eind zh zl bit (d-pointer) 23 16 15 8 7 0
12 8077b?avr?06/08 xmega a 3.11 accessing 16-bits registers the avr data bus is 8-bit so accessing 16-bit registers requires atomic operations. these regis- ters must be byte-accessed using two read or wr ite operations. due to this each 16-bit register uses an 8-bit register for temporary storing the hi gh byte during each write or read. a 16-bit reg- ister is connected to the 8-bit bus and a temporar y register using a 16-bit bus. this ensures that the low- and high-byte of 16-bit registers is always accessed simultaneously when reading or writing the register. for a write operation, the low-byte of the 16-bit register must be written before the high-byte. the low-byte is then written into the temporary register. when the high-byte of the 16-bit register is written, the temporary register is copied into the low-byte of the 16-bit register in the same clock cycle. for a read operation, the low-byte of the 16-bit register must be read before the high-byte. when the low byte register is read by the cpu, the high byte of the 16-bit register is copied into the temporary register in the same clock cycle as the low byte is read. when the high-byte is read, it is then read from the temporary register. interrupts can corrupt the timed sequence if the interrupt is triggered and try to access the same 16-bit register during an atomic 16-bit read/write operations. to prevent this, interrupts can be disabled when writing or reading 16-bit registers. the temporary registers can also be read and written directly from user software. 3.11.1 accessing 24- and 32-bit registers for 24- and 32-bit registers the read and write access is done in the same way as described for 16-bit registers, except there are two temporary registers for 24-bit register and three for 32-bit registers. the least significant byte must be wri tten first when doing a write, and read first when doing a read. 3.12 configuration change protection system critical i/o register settings are protected from accidental modification. the spm instruc- tion is protected from accidental execution, and the lpm instruction is protected when reading the fuses and signature row. this is handled globally by the configuration change protection (ccp) register. changes to the protected i/o regi sters or bit, or execution of the protected instructions are only possible af ter the cpu writes a signature to the ccp register. the different signatures is described the register description. there are 2 mode of operation, one for protected i/o registers and one for protected spm/lpm. 3.12.1 sequence for write operation to protected i/o registers 1. the application code writes the signature for change enable of protected i/o registers to the ccp register. 2. within 4 instruction cycles, the application code must write the appropriate data to the protected register. most protected registers also contain a write enable/change enable bit. this bit must be written to one in the same operation as the data is written. the pro- tected change is immediately disabled if t he cpu performs write operations to the i/o register or data memory, or if the instruction spm, lpm or sleep is executed.
13 8077b?avr?06/08 xmega a 3.12.2 sequence for execution of protected spm/lpm 1. the application code writes the signature for execution of protected spm/lpm to the ccp register. 2. within 4 instruction cycles, the application code must execute the appropriate instruc- tion. the protected change is immediately disabled if the cpu performs write operations to the data memory, or if sleep is executed. once the correct sig nature is written by the cp u, interrupts will be igno red for the configuration change enable period. any interrupt request (inc luding non-maskable interrupts) during the cpp period will set the corresponding interrupt flag as normal and the request is kept pending. after the cpp period any pending interrupts are executed according to their level and priority. dma requests are still handled, but do not influence t he protected confi guration change enable period. a signature written by the dma is ignored. 3.13 fuse lock for some system critical features it is possible to program a fuse to disable all changes in the associated i/o control registers. if this is done, it will not be po ssible to change the registers from the user software, and the fuse can only be reprogrammed using an external programmer. details on this are described in the data sheet module where this feature is available. 3.14 register description 3.14.1 ccp - configuration change protection register ? bit 7:0 - ccp[7:0] - configuration change protection the ccp register must be written with the correct signature to enable change of the protected i/o register or execution of the protected instruction for a maximum of 4 cpu instruction cycles. all interrupts are ignored during these cycles. after these cycles interrupts automatically handled again by the cpu, and any pending interrupts will be exec uted according to th eir level and prior- ity. when the protected i /o register signatur e is written, ccp[0] will read as one as long as the protected feature is enabled. similarly when the protected spm/lpm signature is written ccp[1] will read as one as long as the protected feature is enabled. ccp[7:2] will always be read as zero. table 3-1 on page 13 shows the signature for the various modes. 3.14.2 rampd - extended direct addressing register this register is concatenated with the operand for direct addressing (lds/sts) of the whole data memory space on devices with more than 64k bytes of data memory. when accessing bit 76543210 +0x04 ccp[7:0] ccp read/writewwwwwwr/wr/w initial value 00000000 table 3-1. modes of cpu change protection signature group configuration description 0x9d spm protected spm/lpm 0xd8 ioreg protected io register
14 8077b?avr?06/08 xmega a data addresses below 64k bytes, this register is no t in use. this register is not available if the data memory including external memory is less than 64k bytes. ? bit 7:0 ? rampd[7:0]: extended direct addressing bits these bits holds the 8 msb of the 24-bit address created by rampd and the 16-bit operand. only the number of bits required to address t he available data memory is implemented for each device. unused bits will always read as zero. 3.14.3 rampx - extended x-pointer register this register is concatenated with the x-register for indirect addressing (ld/ldd/st/std) of the whole data memory space on devices with more t han 64k bytes of data memory. when access- ing data addresses below 64k bytes, this register is not in use. this register is not available if the data memory including external memory is less than 64k bytes. ? bit 7:0 ? rampx[7:0]: extended x-pointer address bits these bits holds the 8 msb of the 24-bit addr ess created by rampx and the 16-bit x-register. only the number of bits required to address t he available data memory is implemented for each device. unused bits will always read as zero. 3.14.4 rampy - extended y-pointer register this register is concatenated with the y-register for indirect addressing (ld/ldd/st/std) of the whole data memory space on devices with more t han 64k bytes of data memory. when access- ing data addresses below 64k bytes, this register is not in use. this register is not available if the data memory including external memory is less than 64k bytes. ? bit 7:0 ? rampy[7:0]: extended y-pointer address bits these bits hold the 8 msb of the 24-bit addres s created by rampy and the 16-bit y-register. only the number of bits required to address t he available data memory is implemented for each device. unused bits will always read as zero. 3.14.5 rampz - extended z-pointer register this register is concatenated with the z-register for indirect addressing (ld/ldd/st/std) of the whole data memory space on devices with more than 64k bytes of data memory. rampz is concatenated with the z-register when reading (elpm) program memory locations above the bit 76543210 +0x08 rampd[7:0] rampd read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 +0x09 rampx[7:0] rampx read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 00000000 bit 76543210 +0x0a rampy[7:0] rampy read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 00000000
15 8077b?avr?06/08 xmega a first 64k bytes, and writing (spm) program memory locations above the first 128k bytes of the program memory. when accessing data addressees below 64k bytes, reading program memory locations below 64k bytes and writing program memory locations below 128k bytes, this register is not in use. this register is not available if the data memory including external memory and program mem- ory in the device is less than 64k bytes. ? bit 7:0 ? rampz[7:0]: extended z-pointer address bits these bits holds the 8 msb of the 24-bit address created by rampz and the 16-bit z-register. only the number of bits required to address the available data and program memory is imple- mented for each device. unused bits will always read as zero. 3.14.6 eind - extended indirect register this register is concatenated with the z-regi ster for enabling extended indirect jump (eijmp) and call (ecall) to the whole program memory space devices with more than 128k bytes of program memory. for jump or call to addressees below 128k bytes, this register is not in use. this register is not available if the program me mory in the device is less than 128k bytes. ? bit 7:0 - eind[7:0]: extended indirect address bits these bits holds the 8 msb of the 24-bit address created by eind and the 16-bit z-register. only the number of bits required to access the available program memory is implemented for each device. unused bits will always read as zero. 3.14.7 spl - stack pointer register low the sph and spl register pair represent the 16-bit value sp. the sp holds the stack pointer that point to the top of the stack. after reset, the stack pointer points to the highest internal sram address. only the number of bits required to address th e available data memory including external mem- ory, up to 64k bytes is impl emented for each devic e. unused bits will always read as zero. note: 1. refer to specific device datasheets for exact initial values. ? bit 7:0 - sp[7:0]: stack pointer register low byte these bits hold the 8 lsb of the 16-bits stack pointer (sp). bit 76543210 +0x0b rampz[7:0] rampz read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 00000000 bit 76543210 +0x0c eind[7:0] eind read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 00000000 bit 76543210 +0x0d sp[7:0] spl read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value (1) 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1
16 8077b?avr?06/08 xmega a 3.14.8 sph - stack pointer register high note: 1. refer to specific device datasheets for exact initial values. ? bits 7:0 - sp[15:8]: stack pointer register high byte these bits hold the 8 msb of the 16-bits stack pointer (sp). 3.14.9 sreg - status register the status register (sreg) contains information about the result of the most recently executed arithmetic or logic instruction. ? bit 7 ? i: global interrupt enable the global interrupt enable bit must be set for interrupts to be enabled. if the global interrupt enable register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. the i-bit is not cleared by hardware after an interrupt has occurred. the i-bit can be set and cleared by the application with the sei and cli instructions, as described in the ?instruction set description?. ? bit 6 ? t: bit copy storage the bit copy instructions bit load (bld) and bit store (bst) use the t-bit as source or destina- tion for the operated bit. a bit from a register in the register file can be copied into t by the bst instruction, and a bit in t can be copied into a bit in a register in the register file by the bld instruction. ? bit 5 ? h: half carry flag the half carry flag (h) indicates a half carry in some arithmetic operations. half carry is useful in bcd arithmetic. see the ?instruction set description? for detailed information. ? bit 4 ? s: sign bit, s = n v the sign bit is always an exclusive or between the negative flag n and the two?s complement overflow flag v. see the ?instruction set description? for detailed information. ? bit 3 ? v: two?s complement overflow flag the two?s complement overflow flag (v) supports two?s complement arithmetics. see the ?instruction set description? for detailed information. ? bit 2 ? n: negative flag the negative flag (n) indicates a negative result in an arithmetic or logic operation. see the ?instruction set description? for detailed information. bit 76543210 +0x0e sp[15:8] sph read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value (1) 0/10/10/10/10/10/10/10/1 bit 76543210 +0x0f i t h s v n z c sreg read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 00000000
17 8077b?avr?06/08 xmega a ? bit 1 ? z: zero flag the zero flag (z) indicates a zero result in an arithmetic or logic operation. see the ?instruction set description? for detailed information. ? bit 0 ? c: carry flag the carry flag (c) indicates a carry in an arithmetic or logic operation. see the ?instruction set description? for de tailed information. 3.15 register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page +0x00 reserved - - - - - - - - +0x01 reserved - - - - - - - - +0x02 reserved - - - - - - - - +0x03 reserved - - - - - - - - +0x04 ccp ccp[7:0] 13 +0x05 reserved - - - - - - - - +0x06 reserved - - - - - - - - +0x07 reserved - - - - - - - - +0x08 rampd rampd[7:0] 13 +0x09 rampx rampx[7:0] 14 +0x0a rampy rampy[7:0] 14 +0x0b rampz rampz[7:0] 14 +0x0c eind eind[7:0] 15 +0x0d spl spl[7:0] 15 +0x0e sph sph[7:0] 16 +0x0f sreg i t h s v n z c 16
18 8077b?avr?06/08 xmega a 4. memories 4.1 features ? flash program memory ? one linear address space ? in-system reprogrammable ? self-programming and bootloader support ? application section for application code ? application table section for application code or data storage ? bootloader section for application code or bootloader code ? separate lock bits and protection for all sections ? flexible software crc ? data memory ? one linear address space ? single cycle access from cpu ? sram ? eeprom ? byte or page accessible ? optional memory mapping for direct load/store ? i/o memory ? configuration and status regist er for all peripherals and modules ? 16 bit accessible general purpose regi ster for global va riable or flags ? external memory ? bus arbitration ? safe and deterministic handling of cpu and dma controller priority ? separate buses for sram, eeprom io memory and external memory access 4.2 overview this section describes the different memories in xmega. the avr architecture has two main memory spaces, the program memory and the da ta memory. executable code can only reside in the program memory, while data can be stored both in the program memory and the data memory. the data memory includes both sram , and an eeprom memory for non-volatile data storage. all memory spaces are linear and requ ire no paging. non-volatile memory (nvm) spaces can be locked for further write and read/write operations. this prevents unrestricted access to the application software. a separate memory section contains the fuse bytes. these are used for setting important sys- tem functions, and write access is only possible from an external programmer. 4.3 flash program memory the xmega contains on-chip in-system reprog rammable flash memory for program storage. the flash memory can be accessed for read and write both from an external programmer through the pdi, or from application software running in the cpu. all avr instructions are 16 or 32 bits wide, and each flash location is 16 bits wide. the flash memory in xmega is organized in two main sections, the application section and the boot loader section, as shown in figure 4-1 on page 19 . the sizes of the different sections are fixed,
19 8077b?avr?06/08 xmega a but device dependent. these two sections have separate lock bits and can have different level of protection. the store program memory (spm) instruction used to write to the flash from the application software, will only operate when executed from the boot loader section. the spm instruction is also used for writing the boot lock bits used for software protection. the application section contains an application table section with separate lock settings. this can be used for safe storage of non-volatile data in the program memory. figure 4-1. flash memory sections 4.3.1 application section the application section is the section of the flash that is used for storing the executable applica- tion code. the protection level for the application section can be selected by the boot lock bits for this section. the application section c an not store any boot loader code since the spm instruction cannot be executed from the application section. 4.3.2 application table section the application table section is a part of the application section of the flash that can be used for storing data. the size is identical to the boot loader section. the protection level for the application table section can be selected by the bo ot lock bits for this section. the possibilities for different protection levels on the applicat ion section and the application table section application flash section 0x000000 end rww, end application start nrww, start boot loader flashend read-while-write section no read-while- write section application table flash section boot loader flash section
20 8077b?avr?06/08 xmega a enable safe parameter storage in the program memory. if this section is not used for data, appli- cation code can be reside here. 4.3.3 boot loader section while the application section is used for storing the application code, the boot loader software must be located in the boot loader section since the spm instruction only can initiate program- ming when executing from the this section. the spm instruction can access the entire flash, including the boot loader section itself. the protection level for the boot loader section can be selected by the boot loader lock bits. if this section is not used for boot loader software, appli- cation code can be stored here. 4.3.4 calibration and signature row in addition to the application and boot loader sections mentioned above, the nvm has two sec- tions that are not affected by chip erase. each section is one flash page in size, and is used for parameter storage. one section is for factory programmed device signatures and calibration data for functions such as the oscillators. the values will be stored during factory produc tion test and can be read from an external programming interface and from the application software. some of the calibration values will be automatically loaded to the corr esponding module or peripheral unit during reset. this section can not be erased. see ?nvm signature row? on page 40. for overview of the cali- bration bytes. the other section is fully accessible (read and write) from application software and an external programming interface. this is meant used to store data that should not be erased during chip erase or on chip debug sessions. this section can only be erased using a dedicated erase command. 4.4 fuses and lockbits the fuses are used to set important system function and can only be written from an external programming interface. the application software can read the fuses. the fuses are used to con- figure reset sources such as brown-out detector, spike detector and watchdog, start-up configuration, jtag enable and jtag user id. the lock bits are used to set protection level on the different flash sections. they are used to block read and/or write access of the code. lock bits can be written from en external program- mer and from the application software to set a more strict protection level, but not to set a less strict protection level. chip erase is the only wa y to erase the lock bits. the lock bits are erased after the rest of the flash memory is erased. both fuses and lock bits are reprogrammable like the flash program memory.
21 8077b?avr?06/08 xmega a 4.5 data memory the data memory contains the i/o memory, internal sram, optionally memory mapped eeprom and external memory if available. the data memory is organized as one continuous memory section, as shown in figure 4-2 on page 21 . figure 4-2. data memory map i/o memory, eeprom and sram will always have the same start addresses for all xmega devices. external memory (if exist) will always start at the end of internal sram and end at address 0xffffff. 4.6 internal sram the internal sram is mapped in the data memory space, always starting at hexadecimal address location 0x2000. sram is accessed from the cpu by using the load (ld/lds/ldd) and store (st/sts/std) instructions. start/end address i/o memory (up to 4 kb) eeprom (up to 4 kb) internal sram external memory (0 to 16 mb) 0x000000 0x001000 0xffffff 0x002000 data memory
22 8077b?avr?06/08 xmega a 4.7 eeprom xmega has eeprom memory for non-vo latile data storage. it is a ddressable either in as a sep- arate data space (default), or it can be memory mapped and accessed in normal data space. the eeprom memory supports both byte and page access. 4.7.1 data memory mapped eeprom access the eeprom address space can optionally be m apped into the data memory space to allow highly efficient eeprom r eading and eeprom buffer loading. when doing this eeprom is accessible using load and store instructions . memory mapped eeprom will always start at hexadecimal address location 0x1000. 4.8 i/o memory the status and configuration registers for al l peripherals and modules, including the cpu, are addressable through i/o memory locations in the data memory space. all i/o locations can be accessed by the load (ld/lds/ldd) and store (st/sts/std) instructions, transferring data between the 32 general purpose registers in the register file and the i/o memory. the in and out instructions can address i/o memory locations in the range 0x00 - 0x3f directly. in the address range 0x00 - 0x1f, specific bit manipulat ing and checking instructions are available. the i/o memory definition for an xmega device is shown in "register summary" in the device data sheet. 4.8.1 general purpose i/o registers the lowest 16 i/o memory addresses is reserved for general purpose i/o registers. these reg- isters can be used for storing information, and they are particularly useful for storing global variables and flags, as they are directly bit-accessible using the sbi, cbi, sbis, and sbic instructions. 4.9 external memory xmega has up to 4 ports dedicated to external memory, supporting external sram, sdram, and memory mapped peripherals such as lcd disp lays or other memory mapped devices. for details refer to the external bus interface (ebi) description. the external memory address space will always start at the end of internal sram. 4.10 data memory and bus arbitration as the data memory organized as four separate sets of memories, the different bus masters (cpu, dma controller read and dma controller write) can access different memories at the same time. as figure 4-3 on page 23 shows, the cpu can access the external memory while the dma controller (dmac) is transferring data from internal sram to i/o memory.
23 8077b?avr?06/08 xmega a figure 4-3. bus access 4.10.1 bus priority when several masters request access to the same bus, the bus priority is in the following order (from higher to lower priority) 1. bus master with ongoing access 2. bus master with ongoing burst a. alternating dmac read and dmac write when the they access the same data memory section. 3. bus master requesting burst access a. cpu has priority 4. bus master requesting bus access a. cpu has priority 4.11 memory timing read and write access to the i/o memory takes one cpu clock cycle. write to sram takes one cycle and read from sram takes two cycles. for burst read (dma), new data is available every cycle. eeprom page load (write) takes one cycl e and three cycles are required for read. for burst read, new data is available every second cycle. extern al memory has multi-cycle read and write. the number of cycles depends on type of memory and configuration of the external bus interface. refer to the instruction summary for more details on instructions and instruction timing. 4.12 device id each device has a three-byte device id which identifies the device. these registers identify atmel as the manufacturer of the device and th e device type. a separate register contains the revision number of the device. 4.13 jtag disable it is possible to disable the jtag interface from the applicatio n software. this will prevent all external jtag access to the memory, until t he next device reset or if jtag is enabled again cpu dmac write dmac read i/o memory eeprom external memory sram
24 8077b?avr?06/08 xmega a from the application software. as long as jtag is disabled the i/o pins required for jtag can be used as normal i/o pins. 4.14 io memory protection some features in the device is regarded to be crit ical for safety in some applications. due to this, it is possible to lock the io register related to the event system and the advanced waveform extensions. as long as the lock is enabled, all related io registers are locked and they can not be written from the application software. the lock registers themselves are protected by the configuration change protection mechanism, for details refer to ?configuration change protec- tion? on page 12 . 4.15 register descrip tion - nvm controller 4.15.1 addr2 - non-volatile memory address register 2 the addr2, addr1 and addr0 register s represents the 24-bit value addr. ? bit 7:0 - addr[23:16]: nvm address register byte 2 this register gives the address extended byte when accessing application and boot section. 4.15.2 addr1 - non-volatile memory address register 1 ? bit 7:0 - addr[15:8]: nvm address register byte 1 this register gives the address high byte when accessing either of the memory locations. 4.15.3 addr0 - non-volatile memory address register 0 bit 76543210 +0x02 addr[23:16] addr2 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 +0x01 addr[15:8] addr1 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 +0x00 addr[7:0] addr0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0
25 8077b?avr?06/08 xmega a ? bit 7:0 - addr[7:0]: nvm address register byte 0 this register gives the address low byte when accessing either of the memory locations. 4.15.4 data2 - non-volatile memory data register byte 2 the data2, data1 and addr0 registers represents the 24-bit value data. ? bit 7:0 - data[23:16]: nvm data register 2 this register gives the data value byte 2 when running crc check on application section, boot section or combined. 4.15.5 data1 - non-volatile memory data register 1 ? bit 7:0 - data[15:8]: nvm data register byte 1 this register gives the data value byte 1 when accessing application and boot section. 4.15.6 data0 - non-volatile memory data register 0 ? bit 7:0 - data[7:0]: nvm data register byte 0 this register gives the data value byte 0 when accessing either of the memory locations. 4.15.7 cmd - non-volatile memory command register ? bit 7 - res: reserved this bit is unused and reserved fo r future use. for comp atibility with future devices, always write this bit to zero when this register is written. bit 76543210 +0x06 data[23:16] data2 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 +0x05 data[15:8] data1 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 +0x04 data[7:0] data0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 +0x0a - cmd[6:0] cmd read/write r r r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0
26 8077b?avr?06/08 xmega a ? bit 6:0 -cmd[6:0]: nvm command these bits define the programming commands for the flash. bit six is set for external program- ming commands. see "memory programming data sheet" for programming commands. 4.15.8 ctrla - non-volatile memory control register a ? bit 7:1 - res: reserved bits these bits are unus ed and reserved for future use. for compatibility with futu re devices, always write these bits to zero when this register is written. ? bit 0 - cmdex: non-volatile memory command execute writing this bit to one will execut e the command in the cm d register. this bit is protected by the configuration change protection (ccp) mechanism, refer to ?configuration change protection? on page 12 for details on the ccp. 4.15.9 ctrlb - non-volatile memory control register b ? bit 7:4 - res: reserved bits these bits are unus ed and reserved for future use. for compatibility with futu re devices, always write these bits to zero when this register is written. ? bit 3 - eemapen: eeprom data memory mapping enable writing this bit to one will enable data memo ry mapping of the eeprom section. the eeprom can then be accessed using load and store instructions. ? bit 2 - fprm: flash power reduction mode writing this bit to one will enable power saving for the flash memory. the section not being accessed will be turned off like in sl eep mode. if code is running from applic ation section, the boot loader section will be turned off and wise versa. if access to the section that is turned off is required, the cpu will be halted eq ually long to the start-up time from the idle sleep mode. this bit is protected by the configuration change protection (ccp) mechanism, refer to ?configura- tion change protection? on page 12 for details on the ccp. ? bit 1 - eprm: eeprom power reduction mode writing this bit to one will enable power saving for the eeprom memory. the eeprom will then be powered down equal to entering sleep mode. if access is required, the bus master will be halted equally long as the start-up time from id le sleep mode. this bit is protected by the bit 76543210 +0x0b -------cmdexctrla read/write rrrrrrrs initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 +0x0c - - - - eemapen fprm eprm spmlock ctrlb read/write r r r r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0
27 8077b?avr?06/08 xmega a configuration change protection (ccp) mechanism, refer to ?configuration change protection? on page 12 for details on the ccp. ? bit 0 - spmlock: spm locked the spm locked bit can be written to prevent all further self-programming. the bit is cleared at reset and cannot be cleared from software. this bit is protected by the configuration change protection (ccp) mechanism, refer to ?configuration change protection? on page 12 for details on the ccp. 4.15.10 intctrl - non-volatile memory interrupt control register ? bit 7:4 - res: reserved bits these bits are unus ed and reserved for future use. for compatibility with futu re devices, always write these bits to zero when this register is written. ? bit 3:2 - spmlvl[1:0]: spm ready interrupt level these bits enable the interrupt and select the interrupt level as described in ?interrupts and pro- grammable multi-leve l interrupt controlle r? on page 108 . the interrupt is a level interrupt, which will be triggered when the busy flag in the status is set to logical 0. since the interrupt is a level interrupt no te the following. the interrupt should not be enabled before triggering a nvm command, as the busy flag wont be set before the nvm command is triggered. since the interrupt trigger is a level interrupt, the interrupt should be disabled in the interrupt handler. ? bit 1:0 - eelvl[1:0]: eeprom ready interrupt level these bits enable the eeprom ready interrupt and select the interrupt level as described in ?interrupts and programmable multi-level interrupt controller? on page 108 . the interrupt is a level interrupt, which will be triggered when the bu sy flag in the status is set to logical 0. since the interrupt is a leve l interrupt note the following. the interrupt should not be enabled before triggering a nvm command, as the busy flag wont be set before the nvm command is triggered. since the interrupt trigger is a level interrupt, the interrupt should be disabled in the interrupt handler. 4.15.11 status - non-volatile memory status register bit 76543210 +0x0d - - - - spmlvl[1:0] eelvl[1:0] intctrl read/write r r r r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 7 6 5432 1 0 +0x04 busyfbusy----eeloadfloadstatus read/write r r rrrr r r initial value 0 0 0000 0 0
28 8077b?avr?06/08 xmega a ? bit 7 - nvmbusy: non-volatile memory busy the nvmbsy flag indicates whether the nvm me mory (flash, eeprom, lock-bits) is busy being programmed. once a program operation is started, this flag will be set and it remains set until the program operation is completed. he nvmbsy flag will automatically be cleared when the operation is finished. ? bit 6 - fbusy: flash section busy the fbusy flag indicate whether a flash operation (page erase or page write) is initiated. once a operation is started the fbusy flag is set, and the application section cannot be accessed. the fbusy bit will automatically be cleared when the oper ation is finished. ? bit 5:2 - res: reserved these bits are reserved and will always be read as zero. for compatibility with future devices, always write these bits to zero when this register is written. ? bit 1 - eeload: eeprom page buffer active loading the eeload status flag indicates that the temporary eeprom page buffer has been loaded with one or more data bytes. immediately after an eeprom load command is issued and byte is written to nvmdr, or a memory mapped eeprom buffer load operation is performed, the eeload flag is set, and it remains set until an eeprom page write- or a page buffer flush oper- ation is executed. ? bit 0 - fload: flash page buffer active loading the fload flag indicates that the temporar y flash page buffer has been loaded with one or more data bytes. immediately after a flash load command has been issues and byte is written to nvmdr, the fload flag is set, and it remains set until an application- or boot page write- or a page buffer flush operation is executed. 4.15.12 lockbits - non-volatile memory lock bit register this register is a direct mapping of the nvm lockbits into the io memory space, in order to enable direct read access from the application software. refer to ?lockbits - non-volatile memory lock bit register? on page 33 for description of the lock bits. bit 76543210 +0x07 blbb[1:0] blba[1:0] blbat[1:0] lb[1:0] lockbits read/write rrrrrrrr initial value 1 1 1 1 1 1 1 1
29 8077b?avr?06/08 xmega a 4.16 register description ? nvm fuses and lockbits 4.16.1 fusebyte0 - non-volatile memory fuse byte 0 - jtag user id ? bit 7 - jtaguid[7:0]: jtag user id these fuses can be used to set the default jtag user id for the device. during reset, the jtaguid fuse bits will be loaded into the mcu jtag user id register. 4.16.2 fusebyte1 - non-volatile memory fuse byte1 - watchdog configuration ? bit 7:4 - wdwper[3:0]: watchdog window timeout period the wdwper fuse bits are used to set initia l value of the closed window for the watchdog timer in window mode. during reset these fuse bi ts are automatically written to the wper bits watchdog window mode control register, refer to ?winctrl ? window mode control regis- ter? on page 105 for details. ? bit 3:0 - wdper[3:0]: watchdog timeout period the wdper fuse bits are used to set initial value of the watchdog timeout period. during reset these fuse bits are automatically written to the per bits in the watchdog control register, refer to ?ctrl ? watchdog timer control register? on page 104 for details. 4.16.3 fusebyte2 - non-volatile memory fuse byte2 - reset configuration ? bit 7 - dvsdon: spike detector enable the dvdson fuse bit can be programmed to enable a voltage spike detector. the spike detec- tor will detect fast rising power an d issue a system reset. for deta ils on the spike detector, refer to ?spike detector reset? on page 98 . bit 7 6543210 +0x00 jtaguid[7:0] fusebyte0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0000000 bit 7 6543210 +0x01 wdwper[3:0] wdper[3:0] fusebyte1 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0000000 bit 7 6 543210 +0x02 dvdson bootrst - - bodact[1: 0] bodpd[1:0] fusebyte2 read/write r/w r/w r r r/w r/w r/w r/w initial value 1 1 --1111
30 8077b?avr?06/08 xmega a ? bit 6 - bootrst: boot loader section reset vector the bootrst fuse can be programmed so the reset vector is pointing to the first address in the boot loader flash sect ion. in this case, the device will start executing from the from boot loader flash section after reset. ? bit 5:4 - res: reserved these fuse bits are reserved and will always be read as zero. for compatibility with future devices, always write these bits to zero when this register is written. ? bit 3:2 - bodact[1:0]: bo d operation in active mode the bodact fuse bits set the bod operation mode when the device is in active and idle mode of operation. for details on the bod and bod operation modes refer to ?brown-out detection? on page 97 . ? bit 1:0 - bodpd[1:0]: bod operation in power-down mode the bodpd fuse bits set the bod operation mode in all sleep modes except idle mode. for details on the bod and bod operation modes refer to ?brown-out detection? on page 97 . table 4-1. spike detector fuse dvdson description 0 spike detector enabled 1 spike detector disabled table 4-2. boot reset fuse bootrst reset address 0 reset vector = boot loader reset 1 reset vector = application reset (address 0x0000) table 4-3. bod operation modes in active and idle mode bodact[1:0] description 00 reserved 01 bod enabled in sampled mode 10 bod enabled continuously 11 bod disabled table 4-4. bod operation modes in sleep modes bodact[1:0] description 00 reserved 01 bod enabled in sampled mode 10 bod enabled continuously 11 bod disabled
31 8077b?avr?06/08 xmega a 4.16.4 fusebyte4 - non-volatile memory fuse byte4 - start-up configuration ? bit 7:5 - res: reserved these fuse bits are reserved and will always be read as zero. for compatibility with future devices, always write these bits to zero when this register is written. ? bit: 4 - rstdisbl - external reset disable this fuse can be programmed to disable the external reset pin functionality. when this is done the reset pin will function as a normal i/o pin only, and pulling this pin low will not cause an external reset. ? bit 3:2 - startuptim e[1:0]: start-up time the startuptime fuse bits can be used to set at a programmable timeout period from all reset sources are released and until the internal reset is released from the delay counter. the delay is timed from the 1khz output of the ulp oscillator, refer to ?reset sequence? on page 95 for details. ? bit 1 - wdlock: watchdog timer lock the wdlock fuse can be programmed to lock the watchdog timer configuration. when this fuse is programmed the watchdog timer configuration cannot be changed, and the watchdog timer cannot be disabled from the application software. ? bit 0 - jtagen: jtag enabled the jtagen fuse decides whether or not the jtag interface is enabled. bit 765 4 3 2 1 0 +0x04 - - - rstdisbl startuptime[1 :0] wdlock jtagen fusebyte4 read/write r r r r r/w r/w r/w r/w initial value - - - - 1 1 1 1 table 4-5. start-up time startuptime[1:0] 1khz ulp oscillator cycles 00 64 01 4 10 reserved 11 0 table 4-6. watchdog timer locking wdlock description 0 watchdog timer locked for modifications 1 watchdog timer not locked
32 8077b?avr?06/08 xmega a when the jtag interface is disabled all access through jtag is prohibited, and the device can only be accessed using the program and debug interface (pdi). the jtagen fuse is only available on devices with jtag interface. 4.16.5 fusebyte5 - non-volatile memory fuse byte 5 ? bit 7:4 - res: reserved these bits are reserved and will always be read as zero. for compatibility with future devices, always write these bits to zero when this register is written. ? bit 3 - eesave: eeprom memory is preserved through the chip erase a chip erase command will normal ly erase the flash, eeprom and internal sram. if the eesave fuse is programmed, the eeprom is not erased during ch ip erase. in case eeprom is used to store data independen t of software revision, the eeprom can be pr eserved through chip erase. changing of the eesave fuse bit takes effect im mediately after the write time-out elapses. hence, it is possible to update eesave and perform a chip erase according to the new setting of eesave without leaving and re-entering pr ogramming mode ? bit 2:0 - bodlevel[2:0] - brow n out detection voltage level the bodlevel fuse bits sets th e nominal bod level va lue. during power-on the device is kept in reset until the v cc level has reached the programmed bod level. due to this always ensure that the bod level is set lower than the v cc level, also if the bod is not enabled and used during normal operation, refer to ?reset sources? on page 95 for details. table 4-7. jtag enable jtagen description 0 jtag enabled 1jtag disabled bit 7654 3 2 1 0 +0x05 - - - - eesave bodlevel[2:0] fusebyte5 read/write r r r r r/w r/w r/w r/w initial value - - - - - - - - table 4-8. eeprom memory through chip erase eesave description 0 eeprom is preserved during chip erase 1 eeprom is not preserved during chip erase
33 8077b?avr?06/08 xmega a changing these fuse bits will have no effect until leavi ng programming mode. 4.16.6 lockbits - non-volatile memory lock bit register ? bit 7:6 - blbb[1:0]: boot lock bit boot loader section these bits indicate the locking mode for the boot loader section. even though the blbb bits are writable, they can only be written to a stricter locking. resetting the blbb bits is only possi- ble by executing a chip erase command. table 4-9. bod level nominal values, for actual values refer to the device data sheet. bodlevel normal bod level value (v) 111 1.6v 110 1.8v 101 2.0v 100 2.2v 011 2.4v 010 2.7v 001 2.9v 000 3.2v bit 76543210 +0x07 blbb[1:0] blba[1:0] blbat[1:0] lb[1:0] lockbits read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 1 1 1 1 1 1 1 1 table 4-10. boot lock bit for the boot loader section blbb[1:0] group configuration description 11 nolock3 no lock, no restrictions for spm and (e)lpm accessing the boot loader section. 10 wlock write lock, spm is not allowed to write the boot loader section 01 rlock read lock, (e)lpm executing from the application section is not allowed to read from the boot loader section. if the interrupt vectors ar e placed in the application section, interrupts are disabled while executing from the boot loader section. 00 rwlock read and write lock, spm is not allowed to write to the boot loader section and (e)lpm executing from the application section is not al lowed to read from the boot loader section. if the interrupt vectors ar e placed in the application section, interrupts are disabled while executing from the boot loader section
34 8077b?avr?06/08 xmega a ? bit 5:4 - blba[1:0]: boot lock bit application section these bits indicate the locking mode for the application section. even though the blba bits are writable, they can only be written to a stricter lo cking. resetting the blba bits is only possible by executing a chip erase command. ? bit 3:2 - blbat[1:0]: boot lock bit application table section these bits indicate the locking mode for the application table section. even though the blbat bits are writable, they can only be written to a stricter locking. resetting the blbat bits is only possible by executing a chip erase command. table 4-11. boot lock bit for the application section blba[1:0] group conf iguration description 11 nolock3 no lock, no restrictions for spm and (e)lpm accessing the application section. 10 wlock write lock, spm is not allowed to write them application section 01 rlock read lock, (e)lpm executing from the boot loader section is not allowed to read from the application section. if the interrupt vectors ar e placed in the boot loader section, interrupts are disabled while executing from the application section. 00 rwlock read and write lock, spm is not allowed to write to the application section and (e)lpm executing from the boot loader section is not allowed to read from the application section. if the interrupt vectors ar e placed in the boot loader section, interrupts are disabled while executing from the application section. table 4-12. boot lock bit for the application table section blbat[1:0] group configuration description 11 nolock3 no lock, no restrictions for spm and (e)lpm accessing the application table section. 10 wlock write lock, spm is not allowed to write the application ta b l e 01 rlock read lock, (e)lpm executing from the boot loader section is not allowed to read from the application table section. if the interrupt vectors ar e placed in the boot loader section, interrupts are disabled while executing from the application section. 00 rwlock read and write lock, spm is not allowed to write to the application table section and (e)lpm executing from the boot loader section is not allowed to read from the application table section. if the interrupt vectors ar e placed in the boot loader section, interrupts are disabled while executing from the application section.
35 8077b?avr?06/08 xmega a ? bit 1:0 - lb[1:0]: lock bits these bits indicate the locking mode for the flash and eeprom in programming mode. these bits are writable only through an external prog ramming interface. resetting the lock bits is only possible by executing a chip erase command. 4.17 register description ? general purpose i/o memory 4.17.1 gpiorn ? general purpose i/o register n this is a general purpose register that can be used to store data such as global variables in the bit accessible i/o memory space. 4.18 register descripti on ? external memory refer to ?ebi - external bus interface? on page 243 . 4.19 register d escription ? mcu 4.19.1 devid2 - mcu de vice id register 2 the devid2, devid1 and devid0 registers represents the 24-bit register devid. ? bit 7:0 - devid[23:16]: mcu device id byte 2 byte 2 of the device id indicates the device number. refer to device data sheet for actual id. table 4-13. boot lock bit for the boot section lb[1:0] group configuration description 11 nolock3 no lock, no memory locks enabled. 10 wlock write lock, programming of the flash and eeprom is disabled for the programming interface. fuse bits are locked for write from the programming interface. 00 rwlock read and write lock, programming and read/verification of the fl ash and eeprom is disabled for the programming interface. the lock bits and fuses are locked for read and write from the programming interface. bit 76543210 +n gpiorn[7:0] gpiorn read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 +0x02 devid[23:1 6] devid2 read/write rrrrrrrr initial value 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0
36 8077b?avr?06/08 xmega a 4.19.2 devid1 - mcu de vice id register 1 ? bit 7:0 - devid[15:8]: mcu device id byte 1 byte 1 of the device id indicates the flash size of the device. refer to device data sheet for actual id. 4.19.3 devid0 - mcu de vice id register 0 ? bit 7:0 - devid[7:0]: mcu device id byte 0 this byte will always be read as 0x1e. this indicates manu factured by atmel. 4.19.4 revid - mcu revision id ? bit 7:4 - res: reserved these bits are reserved and will always read as zero. for compatibility with future devices, always write these bits to zero when this register is written. ? bit 3:0 - revid[3:0]: mcu revision id these bits contains the device revision. 0=a, 1=b and so on. refer to device data sheet for actual id. 4.19.5 jtaguid ? jtag user id bit 76543210 +0x01 devid[15:8] devid1 read/write rrrrrrrr initial value 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 bit 76543210 +0x00 devid[7:0] devid0 read/write rrrrrrrr initial value 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 bit 76543210 +0x03 - - - - revid[3:0] revid read/write rrrrrrrr initial value 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 bit 76543210 +0x04 jtaguid[7:0] jtaguid read/write rrrrrrrr initial value 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0
37 8077b?avr?06/08 xmega a ? bit 7:0 - jtaguid[7:0]: jtag user id the jtaguid can be used to identify two devices with identical device id in a jtag scan chain. the jtaguid will during reset automatically be loaded from flash and placed in these registers. 4.19.6 mcucr ? mcu control register ? bit 7:1 - res: reserved these bits are unus ed and reserved for future use. for compatibility with futu re devices, always write these bits to zero when this register is written. ? bit 0 - jtagd: jtag disable setting this bit will disable the jtag interface. 4.19.7 evsyslock ? event system lock register ? bit 7:5 - res: reserved these bits are reserved and will always be read as zero. for compatibility with future devices, always write these bits to zero when this register is written. ? bit 4 - evsys1lock: writing this bit to one will lock all registers in th e event system related to event channe ls 4 to 7 for further modifications. the following regist ers in the event system are locked: ch4mux, ch4ctrl, ch5mux, ch5ctrl, ch6mux, ch6ctrl , ch7mux, ch7ctrl. this bit is pro- tected by the configuration change protec tion mechanism, for details refer to ?configuration change protection? on page 12 . ? bit 3:1 - res: reserved these bits are reserved and will always be read as zero. for compatibility with future devices, always write these bits to zero when this register is written. ? bit 0 - evsys0lock: writing this bit to one will lock all registers in th e event system related to event channe ls 0 to 3 for further modifications. the following regist ers in the event system are locked: ch0mux, ch0ctrl, ch1mux, ch1ctrl, ch2mux, ch2ctrl , ch3mux, ch3ctrl. this bit is pro- tected by the configuration change protec tion mechanism, for details refer to ?configuration change protection? on page 12 . bit 76543210 +0x06 - ------ jtagd mcucr read/write rrrrrrrr/w initial value 0 0 0 0 0 0 0 0 bit 765 4 321 0 +0x08 ??? evsys1lock ??? evsys0lock evsys_lock read/write r r r r/w r r r r/w initial value 0 0 0 0 0 0 0 0
38 8077b?avr?06/08 xmega a 4.19.8 awexlock ? advanced waveform extension lock register ? bit 7:3 - res: reserved these bits are reserved and will always be read as zero. for compatibility with future devices, always write these bits to zero when this register is written. ? bit 2 - awexelock: advanced waveform extension lock for t/c e writing this bit to one will lock all registers in the awex module for timer/counter e for further modifications. this bit is protected by the configuration change protection mechanism, for details refer to ?configuration change protection? on page 12 . ? bit 1 - res: reserved this bit is reserved and will a lways be read as zero. for compat ibility with future devices, always write this bit to zero when this register is written. ? bit 0 - awexclock: advanced waveform extension lock for t/c c writing this bit to one will lock all registers in the awex module for timer/counter c for further modifications. this bit is protected by the configuration change protection mechanism, for details refer to ?configuration change protection? on page 12 . bit 76543 2 1 0 +0x09 ????? awexelock ? awexclock awex_lock read/write rrrrr r/w r r/w initial value 0 0 0 0 0 0 0 0
39 8077b?avr?06/08 xmega a 4.20 register summary 4.20.1 nvm controller (flash and eeprom) 4.20.2 nvm fuses and lockbits 4.20.3 general purpose i/o registers address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page +0x00 addr0 nvm address byte 0 24 +0x01 addr1 nvm address byte 1 24 +0x02 addr2 nvm address byte 2 24 +0x03 reserved +0x04 data0 nvm data byte 0 25 +0x05 data1 nvm data byte 1 25 +0x06 data2 nvm data byte 2 25 +0x07 reserved +0x08 reserved +0x09 reserved +0x0a cmd cmd[6:0] 25 +0x0b ctrla cmdex 26 +0x0c ctrlb eemapen fprm eprm spmlock 26 +0x0d intctrl spmlvl[1:0] eelvl[1:0] 27 +0x0e reserved +0x0f status nvmbusy fbusy eeload fload 27 +0x10 lockbits blbb[1:0] blba[1:0] blbat[1:0] lb[1:0] 28 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page +0x00 fusebyte0 jtaguid 29 +0x01 fusebyte1 wdwper3:0] wdper[3:0] 29 +0x02 fusebyte2 dvsdon bootrs t bodact[1:0] bodpd[1:0] 29 +0x03 reserved +0x04 fusebyte4 rstdisbl startuptime[1:0] wdlock jtagen 31 +0x05 fusebyte5 eesave bodlevel[2:0] 32 +0x06 reserved +0x07 lockbits blbb[1:0] blba[1:0] blbat[1:0] lb[1:0] 33 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page +0x00 gpior0 gpior[7:0] 35 +0x01 gpior1 gpior[7:0] 35 +0x02 gpior2 gpior[7:0] 35 +0x03 gpior3 gpior[7:0] 35 +0x04 gpior4 gpior[7:0] 35 +0x05 gpior5 gpior[7:0] 35 +0x06 gpior6 gpior[7:0] 35 +0x07 gpior7 gpior[7:0] 35 +0x08 gpior8 gpior[7:0] 35 +0x09 gpior9 gpior[7:0] 35 +0x0a gpior10 gpior[7:0] 35 +0x0b gpior11 gpior[7:0] 35 +0x0c gpior12 gpior[7:0] 35 +0x0d gpior13 gpior[7:0] 35 +0x0e gpior14 gpior[7:0] 35 +0x0f gpior15 gpior[7:0] 35
40 8077b?avr?06/08 xmega a 4.20.4 mcu registers 4.20.5 nvm signature row address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page +0x00 devid0 devid[7:0] 36 +0x01 devid1 devid[15:8] 36 +0x02 devid2 devid[23:16] 35 +0x03 revid ? ? ? ? revid[3:0] 36 +0x04 jtaguid jtaguid[7:0] 36 +0x05 reserved ? ? ? ? ? ? ? ? +0x06 mcucr ? ? ? ? ? ? ? jtagd 40 +0x07 reserved ? ? ? ? ? ? ? ? +0x08 evsyslock ? ? ? evsys1loc ? ? ? evsys0lock +0x09 awexlock ? ? ? ? ? awexelock ? awexclock +0x0a reserved ? ? ? ? ? ? ? ? +0x0b reserved ? ? ? ? ? ? ? ? word address autoloaded high byte low byte page +0x00 y reserved rcosc2 mhz calib +0x01 y rcosc 32 mhz calib rcosc 32768 khz calib +0x02 n reserved reserved +0x03 n reserved reserved +0x04 n lot number at sort, byte 1, ascii lot number at sort, byte 0, ascii +0x05 n lot number at sort, byte 3, ascii lot number at sort, byte 2, ascii +0x06 n lot number at sort, byte 5, ascii lot number at sort, byte 4, ascii +0x07 n reserved reserved +0x08 n reserved wafer number +0x09 n wafer coordinate y wafer coordinate x +0x0a n reserved reserved +0x0b n reserved reserved +0x0c n reserved reserved +0x0d n reserved reserved +0x0e n reserved reserved +0x0f n reserved reserved +0x10 n adca calib byte 1 adca calib byte 0 +0x11 n adca calib byte 3 adca calib byte 2 +0x12 n adcb calib byte 1 adcb calib byte 0 +0x13 n adcb calib byte3 adcb calib byte 2 +0x14 n reserved reserved +0x15 n reserved reserved +0x16 n reserved reserved +0x17 n reserved reserved +0x18 n daca calib byte 1 daca calib byte 0 +0x19 n dacb calib byte 1 dacb calib byte 0 +0x1a n reserved reserved +0x1b n reserved reserved +0x1c n reserved reserved +0x1d n reserved reserved +0x1e n reserved reserved +0x1f n reserved reserved
41 8077b?avr?06/08 xmega a 5. dmac - direct memory access controller 5.1 features ? the dma controller allows high-speed transfers with mini mal cpu intervention ? from one memory area to another ? from memory area to peripheral ? from peripheral to memory area ? from peripheral to another peripheral ? four dma channels with separate ? transfer triggers ? interrupt vectors ? addressing modes ? from 1 byte to 16m bytes data transfer in a single transaction ? up to 64 kbyte block transfers with repeat ? 1, 2, 4, or 8 byte burst transfers ? internal and external transfer triggers ? multiple addressing modes ? static ?increment ? decrement ? optional reload of source and dest ination address at the end of each ?burst ?block ? transaction ? optional interrupt on end of transaction ? programmable channel priority 5.2 overview the xmega direct memory access (dma) controller is a highly flexible dma controller capable of transferring data between memories and peripherals with minimal cpu intervention. the dma controller has flexible channel priority selection, several addressing modes, double buffer- ing capabilities and large block sizes. the dma controller can move data between memories and peripherals, between memories and between peripherals. there are four dma channels that have individual source, destination, triggers and block sizes. the different channels also have individual cont rol settings and individual interrupt settings and interrupt vectors. interrupt requests may be generated both when a transaction is complete or if the dma controller detects an error on a dma channel. when a dma channel requests a data transfer, the bus arbiter will wait until the avr core is not using the data bus and permit the dma controller to transfer data. transfers are done in bursts of 1, 2, 4 or 8 bytes. addressing can be static, incremental or decremental. automatic reload of source and/or destination address can be done after each burst transfer, block transfer, when transmission is complete, or disabled. both application software, peripherals and events can trigger dma transfers.
42 8077b?avr?06/08 xmega a 5.3 dma transaction a complete dma read and write operation between memories and/or peripherals is called a dma transaction. a transaction is done in data bloc ks and the size of the transaction (number of bytes to transfer) is selectable from software and controlled by the block size and repeat counter settings. each block transfer is divided into smaller bursts. 5.3.1 block transfer and repeat the size of the block transfer is set by the block transfer count register, and can be anything from 1 byte to 64 kbytes. a repeat counter can be enabled to set a number of repeated block transfers before a transac- tion is complete. the repeat is from 1 to 255 and unlimited repeat count can be achieved by setting the repeat count to zero. 5.3.2 burst transfer as the avr core and dma controller use the same data buses a block transfer is divided into smaller burst transfers. the burst transfer is selectable to 1, 2, 4, or 8 bytes. this means that, if the dma acquires a dat a bus and a transfe r request is pending it will occupy the bus until all bytes in the burst transfer is transferred. a bus arbiter controls when the dma controller and the avr core can use the bus. the core always has priority, so as long as the core request access to the bus, any pending burst transfer must wait. the core requests bus access when it executes an instruction that write or read data to sram, io memory, eeprom and the external bus interface. for more details on memory access bus arbitrat ion, refer to ?data memory? on page 21 . figure 5-1. dma transaction. 5.4 transfer triggers dma transfers can only be started when a dma transfer request is detected. a transfer request can be triggered from software, from an external trigger source (peripheral) or from an event. there are dedicated source trigger selections for each dma channel. the available trigger sources may vary from device to device, depending on the modules or peripherals that exist in the device. using a transfer trig ger for a module or peripherals that does not exist will have no effect, for a list of all transfer triggers refer to ?trigsrc - dma channel trigger source? on page 50 . four-byte burst mode block size: 12 bytes repeat count: 2 burst transfer block transfer dma transaction
43 8077b?avr?06/08 xmega a by default, a trigger starts a block transfer operation. the transfer continues until one block is transferred. when the block is tr ansferred, the c hannel will wait for the next trigger to arrive before it start transferring the next block. it is possible to select the trigger to start a burst transfer instead of a block transfer. this is called a single shot transfer. a new trigger will then start a new burst transfer. when repeat mode is enabled, the start of transfer of the next block does not require a transfer trigger. it will start as soon as the prev ious block is done. if the trigger source generates a transfer request during an ongoing transfer this will be kept pending, and the transfer can start when the ongoing one is done. only one pending transfer can be kept, so if the trigger source generates more transfer requests when one is already pend- ing, these will be lost. 5.5 addressing the source and destination address for a dma transfer can either be static, incremental or dec- remental with individual selections for s ource and destination. when address increment or decrement is used, the default behaviour is to update the address after each access. the origi- nal source and destination address is stored by the dma controller, so the source and destination addresses can be individually configured to be reloaded at the following points: ? end of each burst transfer ? end of each block transfer ? end of transaction ? never reload 5.6 priority between channels if several channels request data transfer at the same time a priority scheme is available to deter- mine what channel is allowed to transfer data. application software can decide whether one or more channels should have a fixed priority or if a round robin scheme should be used. a round robin scheme means that the chann el that last transferred dat a will have the lowest priority. 5.7 double buffering to allow for continuous transfer, two channels can be interlinked so that the second takes over the transfer when the first is finished and vice versa. this is called double buffering. when a transmission is completed for the first channel, the second channel is enabled. when a request is detected on the second channel, the transfer starts and when this is completed the first chan- nel is enabled again. 5.8 transfer buffers each dma channel has an internal transfer buffer that is used for 2, 4 and 8 byte burst transfers. when a transfer is triggered, a dma channel will wa it until the transfer bu ffer contains two bytes before the transfer starts. for 4 or 8 byte transfer, any remaining bytes is transferred as soon as they are ready for a dma channel. the buffer is used to reduce the time the dma controller occupy the bus. when the dma controller or a dma channel is disabled from software, any remaining bytes in the buffer will be transferred before the dma controller or dma channel is disabled. this ensures that the source and destination address registers are kept synchronized.
44 8077b?avr?06/08 xmega a 5.9 error detection the dma controller can detect erroneous operati on. error conditions are detected individually for each dma channel, and the error conditions are: ? write to memory mapped eeprom memory locations. ? reading eeprom memory when the eepr om is off (sleep entered). ? dma controller or a busy channel is disabled in software during a transfer. 5.10 software reset both the dma controller and a dma channel can be reset from the user software. when the dma controller is reset, all registers associat ed with the dma controlle r is cleared. a software reset can only be done when the dma controller is disabled. when a dma channel is reset, all registers associated with the dma channel are cleared. a software reset can only be done when the dma channel is disabled. 5.11 protection in order to insure safe operation some of the channel registers are protected during a transac- tion. when the dma channel busy flag (chnbusy ) is set for a channel, the user can only modify these registers and bits: ? ctrl register ? intflags register ? temp registers ? chen, chrst, trfreq, repeat bits of the channel ctrl register ? trigsrc register 5.12 interrupts the dma controller can generate interrupts when an error is detected on a dma channel or when a transaction is complete for a dma channel. each dma channel has a separate interrupt vector, and there are different interrupt flags for error and transaction complete. if repeat is not enabled the transaction complete flag is set at the end of the block transfer. if unlimited repeat is enabled, the transaction comple te flag is also set at the end of each block transfer.
45 8077b?avr?06/08 xmega a 5.13 register descrip tion ? dma controller 5.13.1 ctrl - dma control register ? bit 7 - enable: dma enable setting this bit enables the dma controller. if the dma controller is enabled and this bit is writ- ten to zero, the enable bit is not cleared before the internal transfer buffer is empty and the dma data transfer is aborted. ? bit 6 - reset: dma software reset setting this bit enables the software reset. this bit is automatically cleared when reset is com- pleted. this bit can only be set when the dma controller is disabled (enable = 0). ? bit 5:4 - res: reserved these bits are unus ed and reserved for future use. for compatibility with futu re devices, always write these bits to zero when this register is written. ? bit 3:2 - dbufmode[1:0]: dma double buffer mode these bits enables the double buffer on the different channels according to table 5-1 . ? bit 1:0 - primode[1:0]: dma channel priority mode these bits determine the internal channel priority according to table 5-2 . bit 76543210 +0x00 enable reset - - dbufmode[1:0] primode[1:0] ctrl read/write r/w r/w r r r/w r/w r/w r/w initial value00000000 table 5-1. dma double buffer settings dbufmode[1:0] group co nfiguration description 00 disabled no double buffer enabled 01 ch01 double buffer enabled on channel0/1 10 ch23 double buffer enabled on channel2/3 11 ch01ch23 double buffer enabled on channel0/1 and channel2/3 table 5-2. dma channel priority settings primode[1:0] group configuration description 00 rr0123 round robin 01 ch0rr123 channel0 > round robin (channel 1, 2 and 3) 10 ch01rr23 channel0 > channel1 > round robin (channel 2 and 3) 11 ch0123 channel0 > channel1 > channel2 > channel3
46 8077b?avr?06/08 xmega a 5.13.2 intflags - dma interrupt status register ? bit 7:4 - chnerrif[3:0]: dma channel n error interrupt flag if an error condition is detect ed on dma channel n, the chnerri f flag will be set. writing a one to this bit location will clear the flag. ? bit 3:0 - chntrnfif[3:0]: dma channel n transaction complete interrupt flag when a transaction on channel n has been completed, the chntrfif flag will set. if unlimited repeat count is enabled, this flag is read as one after each block transfer. writing a one to this bit location will clear the flag. 5.13.3 status - dma status register ? bit 7:4 - chnbusy[3: 0]: dma channel busy when channel n starts a dma tran saction, the chnbusy flag will be read as o ne. this flag is automatically cleared when the dma channel is disabled, when the channel n transaction com- plete interrupt flag is set or if the dma channel n error interrupt flag is set. ? bit 3:0 - chnpend[3:0]: dma channel pending if a block transfer is pending on dma channel n, the chnpend flag will be read as one. this flag is automatically cleared when the block transfer starts, or if the transfer is aborted. 5.13.4 temph - dma temporary register high ? bit 7:0 - temp[7:0]: dma temporary register this register is used when reading and writing 24-bit registers in the dma controller. byte 2 of the 24-bit register is stored when it is written by the cpu. byte 2 of the 24-bit register is stored here when byte 1 is read by the cpu. this register can also be read and written from the user software. reading and writing 24-bit register requires special attention, for details refer to ?accessing 16- bits registers? on page 12 . bit 7654 3 2 1 0 +0x04 ch3errif ch2errif ch1errif ch0 errif ch3trnfif ch2trnfif ch1trnfif ch0trnfif intflags read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 +0x05 ch3busy ch2busy ch1busy ch0busy ch3pend ch2pend ch1pend ch0pend status read/writerrrrrrrr initial value 0 0 0 0 0 0 0 0 bit 76543210 +0x07 dmtemp[15:8] temph read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0
47 8077b?avr?06/08 xmega a 5.13.5 templ - dma temporary register low ? bit 7:0 - temp[7:0]: dma temporary register 0 this register is used when reading 24- and 16-bit registers in the dma controller. byte 1 of the 16/24-bit registers is stored here when it is written by the cpu. byte 1 of the 16/24-bit registers are stored when byte 0 is read by the cpu. this register can also be read and written from the user software. reading and writing 16- and 24-bit registers requi res special attention. please see detailed description in the avr core manual. 5.14 register descr iption ? dma channel 5.14.1 ctrla - dma channe l control register a ? bit 7- chen: dma channel enable setting this bit enables the dma channel. this bi t is automatically cleared when the transaction is completed. if the dma channel is enabled and th is bit is written to zero, the chen bit is not cleared before the internal transfer buffer is empty and the dma transfer is aborted. ? bit 6 - chrst: dma channel software reset setting this bit enables the channel reset. this bi t is automatically cleared when reset is com- pleted. this bit can only be set when the dma channel is disabled (chen = 0). ? bit 5 - repeat: dma channel repeat mode setting this bit enables the repeat mode. in repeat mode, this bit is cleared by hardware in the beginning of the last block transfer. the repcnt register should be configured before setting the repeat bit. ? bit 4 - trfreq: dma channel transfer request setting this bit requests a data transfer on the dma channel. this bit is automatically cleared at the beginning of the data transfer. ? bit 3 - res: reserved this bit is unused and reserved fo r future use. for comp atibility with future devices, always write this bit to zero when this register is written. bit 76543210 +0x06 dmtemp[7:0] templ read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 +0x00 chen chrst repeat trfreq - s ingle burstlen[1:0] ctrla read/write r/w r/w r/w r/w r r/w r/w r/w initial value00000000
48 8077b?avr?06/08 xmega a ? bit 2 - single: dma channel single shot data transfer setting this bit enables the single shot mode. the channel will then do a burst transfer of burstlen bytes on the transfer trigger. this bit can not be changed if the channel is busy. ? bit 1:0 - burstlen[1:0]: dma channel burst mode these bits decide the dma channel burst mode according to table 5-3 on page 48 . these bits can not be changed if the channel is busy. 5.14.2 ctrlb - dma channe l control register b ? bit 7- chbusy - dma channel busy when the dma channel starts a dma transact ion, the chbusy flag will be read as one. this flag is automatically cleared when the dma chann el is disabled, when the channel transaction complete interrupt flag is set or if the channel error interrupt flag is set. ? bit 6 - chpend - dma channel pending if a block transfer is pending on the dma channel, the chpend flag w ill be read as one. this flag is automatically cleared when the transfer starts, or if the transfer is aborted ? bit 5 - errif - dma channel error interrupt flag if an error condition is detected the dma channel the errif flag will be set, and the optional interrupt is generated. since the dma channel error interrupt share interrupt address with dma channel transaction complete, the errif will not be cleared when the interrupt vector is exe- cuted. this flag is cleared by writing a one to the bit location. ? bit 4 - trnif - dma channel n tr ansaction complete interrupt flag when a transaction on the dma channel has been completed, the trnif flag will set, and the optional interrupt is generated. when repeat is not enabled the transaction is complete and the trnifr is set after the block transfer. when unlimited repeat is enabled the trnif is also set after each block transfer. since the dma channel transaction complete channel error interrupt share interrupt address with dma channel error interrupt, th e trnif will not be cleared when the interrupt vector is exe- cuted. this flag is cleared by writing a one to the bit location. table 5-3. dma channel burst mode burstlen[1:0] group configuration description 00 1byte 1 byte burst mode 01 2byte 2 bytes burst mode 10 4byte 4 bytes burst mode 11 8byte 8 bytes burst mode bit 76543210 +0x04 chbusy chpend errif trnif errintlvl[1:0] trnintlvl[1:0] ctrlb read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0
49 8077b?avr?06/08 xmega a ? bit [3:2] - errintlvl[1:0]: dm a channel error interrupt level these bits enable the interrupt for dma channel transfer error select the interrupt level as described in ?interrupts and programmable multi-level interrupt controller? on page 108 . the enabled interrupt will trig ger for the conditions when the errif is set. ? bit [1:0] - trnintlvl[1: 0]: dma channel transaction complete interrupt level these bits enable the interrupt for dma channel transaction complete and select the interrupt level as described in ?interrupts and programmable multi-level interrupt controller? on page 108 . the enabled interrupt will tr igger for the conditions when the trnif is set. 5.14.3 addrctrl - dma channe l address control register ? bit 7:6 - srcreload[1:0]: dma channel source address reload these bits decide the dma channel source address reload according to table 5-4 . these bits can not be changed if the channel is busy. ? bit 5:4 - srcdir[1:0]: dma channel source address mode these bits decide the dma channel source address mode according to table 5-5 . these bits can not be changed if the channel is busy. ? bit 3:2 - destreload[1:0]: dma channel destination address reload these bits decide the dma channel destination address reload according to table 5-6 on page 50 . these bits can not be changed if the channel is busy. bit 76543210 +0x02 srcreload[1:0] srcdir[1:0] destre load[1:0] destdir[1:0] addrctrl read/write r/w r/w r/w r/w r r/w r/w r/w initial value00000000 table 5-4. dma channel source address reload settings srcreload[1:0] group conf iguration description 00 none no reload performed. 01 block dma source address register is reloaded with initial value at end of each block transfer. 10 burst dma source address register is reloaded with initial value at end of each burst transfer. 11 transaction dma source address register is reloaded with initial value at end of each transaction. table 5-5. dma channel source address mode settings srcdir[1:0] group conf iguration description 00 fixed fixed. 01 inc increment. 10 dec decrement. 11 - reserved
50 8077b?avr?06/08 xmega a ? bit 1:0 - destdir[1:0]: dma ch annel destination address mode these bits decide the dma channel destination address mode according to table 5-7 on page 50 . these bits can not be changed if the channel is busy. 5.14.4 trigsrc - dma channel trigger source ? bit 7:0 - trigsrc[7:0]: dma channel block trigger source select these bits select which trigger source is used for triggering a transfer on the dma channel. a zero value means that the trigger source is disabled. for each trigger source the value to put in the trigsrc register is the sum of the module or peripheral?s base value, and the offset value for the trigger source in the module or peripherals. table 5-8 on page 51 shows the base value for all module and peripherals. table 5-9 on page 51 to table 5-12 on page 52 shows the offset value for the trigger sources in the differ ent modules and peripheral types. for modules or peripherals which does not exist for a device, the transfer trigger does not exist. refer to the device data sheet for the list of peripherals available. table 5-6. dma channel destination address reload settings destreload[1:0] group configuration description 00 none no reload performed. 01 block dma channel destination address register is reloaded with initial value at end of each block transfer. 10 burst dma channel destination address register is reloaded with initial value at end of each burst transfer. 11 transaction dma channel destination address register is reloaded with initial value at end of each transaction. table 5-7. dma channel destination address mode settings destdir[1:0] group conf iguration description 00 fixed fixed 01 inc increment 10 dec decrement 11 - reserved bit 76543210 +0x03 trigsrc[7:0] trigsrc read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0
51 8077b?avr?06/08 xmega a table 5-8. dma trigger sources, base value for all modules and peripherals trigsrc base value group configuration description 0x00 off software triggers only 0x01 sys system dma triggers base value 0x10 adca adca dma triggers base value 0x15 daca daca dma trigger bas 0x20 adcb adcb dma triggers base value 0x25 dacb dacb dma triggers base value 0x40 tcc0 timer/counter c0 dma triggers base value 0x46 tcc1 timer/counter c1 triggers base value 0x4a spic spi c dma triggers value 0x4b usartc0 usart c0 dma triggers base value 0x4e usartc1 usart c1 dma triggers base value 0x60 tcd0 timer/counter d0 dma triggers base value 0x66 tcd1 timer/counter d1 triggers base value 0x6a spid spi d dma triggers value 0x6b usartd0 usart d0 dma triggers base value 0x6e usartd1 usart d1 dma triggers base value 0x80 tce0 timer/counter e0 dma triggers base value 0x86 tce1 timer/counter e1 triggers base value 0x8a spie spi e dma triggers value 0x8b usarte0 usart e0 dma triggers base value 0x8e usarte1 usart e1 dma triggers base value 0xa0 tcf0 timer/counter f0 dma triggers base value 0xa6 tcf1 timer/counter f1 triggers base value 0xaa spif spi f dma trigger value 0xab usartf0 usart f0 dma triggers base value 0xae usartf1 usart f1 dma triggers base value table 5-9. dma trigger sources, base value for system triggers trgsrc offset value group configuration description +0x00 ch0 event channel 0 +0x01 ch1 event channel 1 +0x02 ch2 event channel 2
52 8077b?avr?06/08 xmega a notes: 1. for dac only channel 0 and 1 exists and can be used as triggers 2. channel 4 equals adc channel 0 to 3 or'ed together. note: 1. cc channel c and d triggers are only available for timer/counter 0. the group configuration is the ?base_offset?, for example tcc1_cca for the timer/counter c1 cc channel a the transfer trigger. 5.14.5 trfcnth - dma channel block transfer count register h the trfcnth and trfcntl register pair re presents the 16-bit value trfcnt. trfcnt defines the number of bytes in a block transfer. the value of trfcnt is decremented after each byte read by the dma channel. when trfcnt reaches zero, the register is reloaded with the last value written to it. reading and writing 16-bit values requires special attention, for details refer to ?accessing 16- bits registers? on page 12 . table 5-10. dma trigger sources, base values for dac and adc triggers trgsrc offset value group configuration description +0x00 ch0 adc/dac channel 0 +0x01 ch1 adc/dac channel 1 +0x02 ch2 (1) adc channel 2 +0x03 ch3 adc channel 3 +0x04 ch4 (2) adc channel 0, 1, 2, 3 table 5-11. dma trigger sources, base values for timer/ counter triggers trgsrc offset value group configuration description +0x00 ovf overflow/underflow +0x01 err error +0x02 cca compare or capture channel a +0x03 ccb compare or capture channel b +0x04 ccc (1) compare or capture channel c +0x05 ccd compare or capture channel d table 5-12. dma trigger sources, base values for usart triggers trgsrc offset value group configuration description 0x00 rxc receive complete 0x01 dre data register empty bit 76543210 +0x05 trfcnt[15:8] trfcnth read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0
53 8077b?avr?06/08 xmega a ? bit 7:0 - trfcnt[15:8]: dma channel n block transfer count register high byte these bits hold the 8 msb of the 16-bits block transfer count. 5.14.6 trfcntl - dma channel bloc k transfer count register l ? bit 7:0 - trfcnt[7:0]: dma channel n block transfer count register low byte these bits hold the 8 lsb of the 16-bits block transfer count 5.14.7 repcnt - dma channe l repeat counter register repcntcounts how many times a block transfer is performed. for each block transfer this reg- ister will be decremented. when repeat mode is enabled (see repeat bit in ?addrctrl - dma channel address con- trol register? on page 49 ), this register is used to control when the transaction is complete. the counter is decremented after each block transfer if the dma has to serve a limited number of repeated block transfers. when repeat mode is enabled the channel is disabled when repcnt reaches zero, and the last block transfer is comp leted. unlimited repeat is achieved by setting this register to zero. 5.14.8 srcaddr2 - dma channel source address 2 srcaddr0, srcaddr1 and srcaddr2 represents the 24-bit value srcaddr, which is the dma channel source address. srcaddr2 is t he most significant byte in the register. srcaddr may be automatically incremented or decremented based on settings in the srcdir bits in ?addrctrl - dma channel address control register? on page 49 . reading and writing 24-bit values require special attention, for details refer to ?accessing 24- and 32-bit registers? on page 12 . ? bit 7:0 - srcaddr[23: 16]: dma channel source address 2 these bits hold byte 2 of the 24-bits source address. bit 76543210 +0x04 trfcnt[7:0] trfcntl read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 +0x06 repcnt[7:0] repcnt read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000001 bit 76543210 +0x0a srcaddr[23:16] srcaddr2 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000
54 8077b?avr?06/08 xmega a 5.14.9 srcaddr1 - dma channel source address 1 ? bit 7:0 - srcaddr[15:8]: dma channel source address 1 these bits hold byte 1 of the 24-bits source address. 5.14.10 srcaddr0 - dma channel source address 0 ? bit 7:0 - srcaddr[7:0]: dma channel source address 0 these bits hold byte 0 of the 24-bits source address. 5.14.11 destaddr2 - dma cha nnel destination address 2 destaddr0, destaddr1 and d estaddr2 represents the 24-bit value destaddr, which is the dma channel destination address. destaddr2 holds the most significant byte in the reg- ister. destaddr may be automatically incremented or decremented based on settings in the destdir bits in ?addrctrl - dma channel address control register? on page 49 . reading and writing 24-bit values require special attention, for details refer to ?accessing 24- and 32-bit registers? on page 12 . ? bit 7:0 - destaddr[23:16]: dm a channel destination address 2 these bits hold byte 2 of the 24-bits source address. 5.14.12 destaddr1 - dma cha nnel destination address 1 ? bit 7:0 - destaddr[15:8]: dma channel destination address 1 these bits hold byte 1 of the 24-bits source address. bit 76543210 +0x09 srcaddr[15:8] srcaddr1 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 +0x08 srcaddr[7:0] srcaddr0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 +0x0e destaddr[23:16] destaddr2 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 +0x0d destaddr[15:8] destaddr1 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000
55 8077b?avr?06/08 xmega a 5.14.13 destaddr0 - dma cha nnel destination address 0 ? bit 7:0 - destaddr[7:0]: dma channel destination address 0 these bits hold byte 0 of the 24-bits source address. 5.15 register summary ? dma controller 5.16 register summary ? dma channel l bit 76543210 +0x0c destaddr[7:0] destaddr0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page +0x00 ctrl enable reset - - dbuf mode[1:0] primode[1:0] 45 +0x01 reserved - - - - - - - - +0x02 reserved - - - - - - - - +0x03 intflags ch3errif ch2erri f ch1errif ch0errif ch3trnfif ch2trnfif ch1trnfif ch0trnfif 46 +0x04 status ch3busy ch2busy ch1busy ch0 busy ch3pend ch2pend ch1pend ch0pend 46 +0x05 reserved - - - - - - - - +0x06 templ temp[7:0] 47 +0x07 temph temp[15:8] 46 +0x10 ch0 offset offset address for dma channel 0 +0x20 ch1 offset offset address for dma channel 0 +0x30 ch2 offset offset address for dma channel 0 +0x40 ch3 offset offset address for dma channel 0 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page +0x00 ctrla chen chrst repeat trfreq - single burstlen 47 0x01 ctrlb chbusy chpend errif trnif errintlvl[1:0] trnintlvl[1:0] 48 +0x02 addctrl srcreload[1:0] srcdir[1: 0] destreload[1:0] destdir[1:0] 49 +0x03 trigsrc trigsrc[7:0] 50 +0x04 trfcntl trfcnt[7:0] 53 +0x05 trfcnth trfcnt[15:8] 52 +0x06 repcnt repcnt[7:0] 53 +0x07 reserved - - - - - - - - +0x08 srcaddr0 srcaddr[7:0] 54 +0x09 srcaddr1 srcaddr[15:8] 54 +0x0a srcaddr2 srcaddr[23:16] 53 +0x0b reserved - - - - - - - - +0x0c destaddr0 destaddr[7:0] 55 +0x0d destaddr1 destaddr[15:8] 54 +0x0e destaddr2 destaddr[23:16] 54 +0x0f reserved - - - - - - - -
56 8077b?avr?06/08 xmega a 6. event system 6.1 features ? inter peripheral commun ication and signalling ? cpu and dma independent operation ? 8 event channels allows for up to 8 signals to be rout ed at the same time ? events can be generated by ? timer/counters (tcxn) ? real time counter (rtc) ? analog to digital converters (adcx) ? analog comparators (acx) ? ports (portx) ? system clock (clk sys ) ? events can be used by ? timer/counters (tcxn) ? analog to digital converters (adcx) ? digital to analog converters (dacx) ? dma controller (dmac) ? advanced features ? manual event generati on from software (cpu) ? quadrature decoding ? digital filtering ? operative in active and idle mode 6.2 overview the event system is a set of features for inter peripheral communication. it enables the possibil- ity for a change of state in one peripheral to automatically trigger actions in other peripherals. what change of state in a peripheral that will trig ger actions in other per ipherals is configurable in software. it is a simple, but powerful system as it allows for autonomous control of peripherals without any use of interrupt, cpu or dma resources. the indication of a change of state in a peripheral is referred to as an event. the events are passed between peripherals using a dedicated routing network called the event routing net- work. figure 6-1 on page 57 shows a basic block diagram of the event system with the event routing network and the peripherals that are connected.
57 8077b?avr?06/08 xmega a figure 6-1. event system block diagram the cpu is not part of the event system, but it indicates that it is possible to manually generate events from software or by using the on-chip debug system. the event system works in active and idle mode. 6.3 events in the context of the event system, an indication that a change of state within a peripheral has occurred is called an event. there are two main types of events: signaling events and data events. signaling events only indicate a change of state while data events contain additional information. the peripheral from where the event origin is called the event generator. within each periph- eral, for example a timer/counter, there can be several event sources, such as a timer compare match or timer overflow. the peripheral using th e event is called the event user, and the action that is triggered is called the event action. figure 6-2. example of event source, generator, user and action adcx dacx event routing network portx cpu acx rtc t/cxn dmac ircom clk sys event routing network | compare match over-/underflow error timer/counter channel sweep single conversion adc event generator event source event user event action event action selection
58 8077b?avr?06/08 xmega a events can be manually generated by writing to the strobe and data registers. 6.3.1 signaling events signaling events are the most basic type of even ts. a signaling event does not contain any infor- mation apart from the indication of a change in a peripheral. most peripherals can only generate and use signaling events. unless otherwise stated, all occurrences of the word 'event' is to be understood as a signaling event. 6.3.2 data events data events differ from signaling events in that they contain additional information that event users can decode to decide event actions based on the receiver information. the event routing network can route all events to all event users. event users that are only meant for using signaling events have limited de code capabilities and ca nnot fully utilize data. how event users decode data events is shown in table 6-1 on page 58 . event users that can utilize data events can also use signaling events. th is is configurable, and is described in the data sheet module for each peripheral. 6.3.3 manually generating events events can be generated manually by writing the data and strobe register. this can be done from software, and by accessing the registers directly during on-chip debugging. the data reg- ister must be written first since writing the st robe register triggers the operation. the data and strobe registers contain one bit for each event channel. bit n corresponds to event chan- nel n. it is possible to generate events on several channels at the same time by writing to several bit locations at once. manually generated events last for on clock cycl e and will overwrite events from other event dur- ing that clock cycle. when manually generati ng events, event channels where no events are entered will let othe r events through. table 6-1 on page 58 shows the different events, how they can be manually generated and how they are decoded. 6.4 event routing network the event routing network routes events between peripherals. it consists of eight multiplexers (chnmux), where events from all event sources are routed into all multiplexers. the multiplex- ers select what event is routed back as input to all peripherals. the output from a multiplexer is referred to as an event channel. for each peripheral it is selectable if and how incoming events should trigger event actions. details on this are described in the data sheet for each peripheral. the event routing network is shown on figure 6-3 on page 59 . table 6-1. manually generated events strobe data data event user signaling event user 0 0 no event no event 0 1 data event 01 no event 1 0 data event 02 signaling event 1 1 data event 03 signaling event
59 8077b?avr?06/08 xmega a figure 6-3. event routing network having eight multiplexers means that it is possible to route up to eight events at the same time. it is also possible to route one event through several multiplexers. not all xmega parts contain all peripherals. this only means that peripheral is not available for generating or using events. the network configuration itself is compatible between all devices. (48) porta portb portc portd porte portf adca adcb daca dacb (portf) tcf0 tcf1 (8) (8) (porte) tce0 tce1 (8) (8) (portd) tcd0 tcd1 (8) (8) (portc) tcc0 tcc1 (8) (8) (8) (8) (8) (16) (16) (16) (16) (13) (4) (4) (8) (8) (8) (8) (8) ac0 ac1 ac2 ac3 rtc (8) (8) (8) (8) (8) (8) ch0mux[7:0] ch1mux[7:0] ch2mux[7:0] ch3mux[7:0] ch4mux[7:0] ch5mux[7:0] ch6mux[7:0] ch7mux[7:0] ch1ctrl[7:0] ch0ctrl[7:0] ch2ctrl[7:0] ch3ctrl[7:0] ch4ctrl[7:0] ch5ctrl[7:0] ch6ctrl[7:0] ch7ctrl[7:0] event channel 7 event channel 6 event channel 5 event channel 4 event channel 3 event channel 2 event channel 1 event channel 0
60 8077b?avr?06/08 xmega a 6.5 event timing an event normally lasts for one clock cycle, but some event sources, such as low level on an i/o pin, have the possibility to generate events c ontinuously. details on this are described in the datasheet for each peripheral, but unless elsewhere stated, an event lasts for one clock cycle only. it takes up to two clock cycles from an event is generated until the event actions in other periph- erals is triggered. it takes one clock cycle from the event happens until it is registered by the event routing network on the first positive clock edge. it takes an additional clock cycle to route the event through the event channel to the event user. 6.6 filtering each event channel includes a digital filter. when this is enabled for an event channel, an event must be sampled a configurable nu mber of system clock cycles before it is accepted. this is pri- marily intended for pin change events. 6.7 quadrature decoder (qdec) the event system includes three quadrature deco ders (qdecs). this enables the event sys- tem to decode quadrature input on i/o pins, and send data events that a timer/counter can decode to trigger the appropriate event action: count up, count down or index/reset. table 6-2 on page 60 summarizes what quadrature decoder data events are available, how they are decoded, and how they can be generated. the qdecs and related features and control and sta- tus register is available for event channel 0, 2 and 4. 6.7.1 quadrature operation a quadrature signal is characterized by having two square waves phase shifted 90 degrees rela- tive to each other. rotational movement can be measured by counting the edges of the two waveforms. the phase relationship between the two square waves determines the direction of rotation. table 6-2. quadrature decoder data events strobe data data event user signaling event user 0 0 no event no event 0 1 index/reset no event 1 0 count down signaling event 1 1 count up signaling event
61 8077b?avr?06/08 xmega a figure 6-4. quadrature signals from a rotary encoder figure 6-4 shows typical quadrature signals from a rotary encoder. the signals qdph0 and qdph90 are the two quadrature signals. when qdph90 leads qdph0, the rotation is defined as positive or forward. when qdph0 leads qdph 90, the rotation is defined as negative, or reverse. the concatenation of the two phase signals is called the quadrature state or the phase state. in order to know the absolute rotary displacement a third index signal (qdindx) can be used. this gives an indication once per revolution. 6.7.2 qdec setup for a full qdec setup th e following is required: ? i/o port pins - quadrature signal input ? the event system - quadrature decoding ? a timer/counter - up, down and optional index count the following procedure should be used for qdec setup: ? choose two successive pins on a port as qdec phase inputs. ? set pin direction for qdph0 and qdph90 as input. ? set pin configuration for qdph0 and qdph90 to low level sense. ? select qdph0 pin as multiplexer input for an event channel, n. ? enable quadrature decoding and digital filtering in the event channel. ? optional: a. setup qdec index (qindx). b. select a third pin for qindx input. c. set pin direction for qindx as input. d. set pin configuration for qindx to sense both edges. e. select qindx as multiplexer input for event channel n+1 f. set the quadrature index enable bit in event channel n+1. g. select the index recognition mode for event channel n+1. ? set quadrature decoding as event action for a timer/counter. ? select event channel n as event source the timer/counter. 00 10 11 01 qdph0 qdph90 qdindx forward direction backward direction 01 11 10 00 1 cycle / 4 states qdph0 qdph90 qdindx
62 8077b?avr?06/08 xmega a ? set the period register of the timer/counter to ('line count' * 4 - 1). (the line count of the quadrature encoder). ? enable the timer/counter by se tting clksel to a clksel_div1. the angle of a quadrature encoder attached to qdph0, qdph90 (and qindx) can now be read directly from the timer/counter count register. if the count register is different from bottom when the index is recognized, the timer/counter erro r flag is set. similarly the error flag is set if the position counter passes bottom without the recognition of the index. 6.8 register description 6.8.1 chnmux ? event channel n multiplexer register . ? bit 7:0 - chnmux[7:0]: channel multiplexer these bits select the event source according to table 6-3 . this table is valid for all xmega devices regardless of if the peripheral is present or not. selecting event sources from peripher- als that are not pres ent will give the same result as when th is register is zero. when this register is zero no events are routed through. manua lly generated events will override the chnmux and be routed to the event channel even if this register is zero. bit 76543210 chnmux[7:0] chnmux read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 00000000 table 6-3. chnmux[7:0] bit settings chnmux[7:4] chnmux[3:0] group configuration event source 0000 0000 none (manually generated events only) 0000 0001 (reserved) 0000 0 0 1 x (reserved) 0000 0 1 x x (reserved) 0000 1000rtc_ovf rtc overflow 0000 1001rtc_cmp rtc compare march 0000 1 0 1 x (reserved) 0000 1 1 x x (reserved) 0001 0000aca_ch0 aca ch annel 0 0001 0001aca_ch1 aca ch annel 1 0001 0010aca_win aca window 0001 0011acb_ch0 acb ch annel 0 0001 0100acb_ch1 acb ch annel 1 0001 0101acb_win acb window 0001 0 1 1 x (reserved)
63 8077b?avr?06/08 xmega a note: 1. the description of how ports generate events are described in section 12.8 ?port event? on page 121 . 0001 1 x x x (reserved) 0010 0 0 n adca_chn adca channel n (n =0, 1, 2 or 3) 0010 0 1 n adcb_chn adcb channel n (n=0, 1, 2 or 3) 0010 1 x x x (reserved) 0011 xxxx (reserved) 0100 xxxx (reserved) 0101 0 n porta_pinn (1) porta pin n (n= 0, 1, 2 ... or 7) 0101 1 n portb_pinn (1) portb pin n (n= 0, 1, 2 ... or 7) 0110 0 n portc_pinn (1) portc pin n (n= 0, 1, 2 ... or 7) 0110 1 n portd_pinn (1) portd pin n (n= 0, 1, 2 ... or 7) 0111 0 n porte_pinn (1) porte pin n (n= 0, 1, 2 ... or 7) 0111 1 n portf_pinn (1) portf pin n (n= 0, 1, 2 ... or 7) 1000 m prescaler_m clk sys divide by m (m=1 to 32768) 1001 xxxx (reserved) 1010 xxxx (reserved) 1011 xxxx (reserved) 1100 0 e see table 6-4 timer/counter c0 event e 1100 1 e see table 6-4 timer/counter c1 event e 1101 0 e see table 6-4 timer/counter d0 event e 1101 1 e see table 6-4 timer/counter d1 event e 1110 0 e see table 6-4 timer/counter e0 event e 1110 1 e see table 6-4 timer/counter e1 event e 1111 0 e see table 6-4 timer/counter f0 event e 1111 1 e see table 6-4 timer/counter f1 event e table 6-4. timer/counter events t/c event event type 0 0 0 tcxn_ovf over-/underflow (x = c, d, e or f) (n= 0 or 1) 0 0 1 tcxn_err error (x = c, d, e or f) (n= 0 or 1 0 1 x (reserved) 1 0 0 tcxn_cca capture or compare a (x = c, d, e or f) (n= 0 or 1 1 0 1 tcxn_cca capture or compare b (x = c, d, e or f) (n= 0 or 1 1 1 0 tcxn_cca capture or compare c (x = c, d, e or f) (n= 0 or 1) 1 1 1 tcxn_cca capture or compare d (x = c, d, e or f) (n= 0 or 1 table 6-3. chnmux[7:0] bit settings (continued) chnmux[7:4] chnmux[3:0] group configuration event source
64 8077b?avr?06/08 xmega a 6.8.2 chnctrl ? event channel n control register . ? bit 7 - res: reserved this bit is reserved and will a lways be read as zero. for compat ibility with future devices, always write this bit to zero when this register is written. ? bit 6:5 - qdirm[1:0]: quadrature decode index recognition mode determines the quadrature state for which a valid index signal is rec ognized and the counter index data event is given according to table 6-5 on page 64 . these bits are only available for ch0ctrl, ch2ctrl and ch4ctrl. ? bit 4 - qdien: quadrature decode index enable when this bit is set the event channel will be used as qdec index so urce, and the index data event will be enabled. these bit is only available fo r ch0ctrl, ch2ctrl and ch4ctrl. ? bit 3 - qden: quadrature decode enable setting this bit enables qdec operation. these bits is only available for ch0ctrl, ch2ctrl and ch4ctrl. ? bit 2:0 - digfilt[2:0]: digital filter coefficient these bits define the length of digital filtering used. events will be passed through to the event channel only when the event source has been active and sampled by the peripheral clock for the number of cycles defined by digfilt. bit 76543210 - qdirm[1:0] qdien qden digfilt[2:0] chnctrl read/write r r/w r/w r/w r/w r/w r/w r initial value00000000 table 6-5. qdirm bit settings qdirm[1:0] index recognition state 0 0 {qdph0, qdph90} = 0b00 0 1 {qdph0, qdph90} = 0b01 1 0 {qdph0, qdph90} = 0b10 1 1 {qdph0, qdph90} = 0b11
65 8077b?avr?06/08 xmega a 6.8.3 strobe ? event strobe register if the strobe register location is written, each event channel will be set according to the strobe[n] and corresponding data[n] bit setting if both are unequal zero. a single event lasting for one peri pheral clock cycl e will be generated. 6.8.4 data ? event data register this register contains the data value when manually generating a data event. this register must be written before the strobe register, for details see ?strobe ? event strobe register? on page 65. table 6-6. digital filter co efficient values digfilt[2:0] group configuration description 000 1sample 1 sample 001 2samples 2 samples 010 3samples 3 samples 011 4samples 4 samples 100 5samples 5 samples 101 6samples 6 samples 110 7samples 7 samples 111 8samples 8 samples bit 76543210 +0x10 strobe[7:0] strobe read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 00000000 bit 76543210 +0x11 data[7:0] data read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 00000000
66 8077b?avr?06/08 xmega a 6.9 register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page +0x00 ch0mux ch0mux[7:0] 62 +0x01 ch1mux ch1mux[7:0] 62 +0x02 ch2mux ch2mux[7:0] 62 +0x03 ch3mux ch3mux[7:0] 62 +0x04 ch4mux ch4mux[7:0] 62 +0x05 ch5mux ch5mux[7:0] 62 +0x06 ch6mux ch6mux[7:0] 62 +0x07 ch7mux ch7mux[7:0] 62 +0x08 ch0ctrl - qdirm[1:0] qdien qden digfilt[2:0] 64 +0x09 ch1ctrl - - - - - digfilt[2:0] 64 +0x0a ch2ctrl - qdirm[1:0] qdien qden digfilt[2:0] 64 +0x0b ch3ctrl - - - - - digfilt[2:0] 64 +0x0c ch4ctrl - qdirm[1:0] qdien qden digfilt[2:0] 64 +0x0d ch5ctrl - - - - - digfilt[2:0] 64 +0x0e ch6ctrl - - - - - digfilt[2:0] 64 +0x0f ch7ctrl - - - - - digfilt[2:0] 64 +0x10 strobe strobe[7:0] 65 +0x11 data data[7:0] 65
67 8077b?avr?06/08 xmega a 7. system clock and clock options 7.1 features ? fast start-up time ? safe run time clock switching ? 4 internal oscillators; 32 mhz, 2 mhz, 32 khz, 32 khz ulp ? 0.4 - 16 mhz crystal oscillator, 32 khz crystal oscillator, external clock ? pll with internal and external cloc k options and 1 to 31x multiplication ? clock prescalers with 1 to 2048x division ? fast peripheral clock ? automatic run-time calibration of internal oscillators ? crystal oscillator failure detection 7.2 overview xmega has an advanced clock system, supporting a large number of clock sources. it incorpo- rates both integrated oscillators , and external crystal oscilla tors and resonators. a high frequency phase locked loop (pll) and clock prescalers can be used to generate a wide range of clock frequencies. a calibration feature (dfll) is available, and can be used for automatic run-time calibration of t he internal oscillators. a crystal osc illator failure monitor can be enabled to issue a non-maskable in terrupt and switch to internal oscillator if t he external oscillator fails. after reset, the device will always start up running from the 2 mhz internal oscillator. in normal operation, the system clock source and prescalers may be changed from software at any time. figure 7-1 on page 68 presents the principal clock system in the xmega. all of the clocks do not need to be active at a given time. the clocks to the cpu and peripherals can be stopped using sleep modes and power reduction registers as described in ?power management and sleep? on page 86 .
68 8077b?avr?06/08 xmega a figure 7-1. the clock system, clock sources and clock distribution 7.3 clock distribution figure 7-1 on page 68 presents the principal clock distribution in the xmega. 7.3.1 system clock - clk sys the system clock is the output from the system clock selection. this is fed into the prescalers that are used to generate all intern al clocks except the asynchronous clock. 7.3.2 clock - clk cpu the cpu clock is routed to the cpu core and non-volatile memory. halting the cpu clock inhibits the cpu from executing instructions. 32 khz int. ulp system clock prescalers 2 mhz int. osc. 32 mhz int. osc. 32 khz int. osc. watchdog timer brown-out detection system clock multiplexer real time counter peripherals ram cpu core non-volatile memory clk per clk sys clk per4 clk per2 clk cpu clk rtc xtal 32 khz xtal 0.4 - 16 mhz external clock pll tosc2 tosc1 xtal2 xtal1 div4
69 8077b?avr?06/08 xmega a 7.3.3 peripheral clock - clk per the majority of peripherals a nd system modules use the perip heral clock. this includes the dma controller, event system, interrupt controller, external bus-interface and ram. this clock is always synchronous to the cpu clock but may run even if the cpu clock is turned off. 7.3.4 peripheral 2x/4x clocks clk per2 /clk per4 modules that can run at two or four times the cpu clock frequency can use the peripheral 2x and peripheral 4x clocks. 7.3.5 asynchronous clock - clk asy the asynchronous clock allows the real time counter (rtc) to be clocked directly from an external 32 khz crystal oscillator, the 32 khz internal oscillator or the ulp oscillator. the dedi- cated clock domain allows operation of this peripheral, even if the device is in a sleep mode where the rest of the clocks are stopped. 7.4 clock sources the clock sources are divided in two main grou ps: internal oscillators and external clock sources. most of the clock sources can be directly enabled and disabled from software, while others are automatically enabled or disabled dependent on current peripheral settings. after reset the device starts up running from the 2 mhz internal oscillator. the dflls and pll are turned off. 7.4.1 internal oscillators the internal osc illators do not require any external components to run. for details on character- istics and accuracy of the internal osc illators refer to th e device data sheet. 7.4.1.1 32 khz ultra low power oscillator this oscillator provides an ap proximate 32 khz clock. the 32 khz ultra low power (ulp) inter- nal oscillator is a very low powe r clock source, and it is not designed for high accuracy.the oscillator employs a built in prescaler prov iding both a 32 khz output and a 1 khz output. the oscillator is automatically enabl ed/disabled when used as clock source for any part of the device. this oscillator can be select ed as clock source for the rtc. 7.4.1.2 32 khz calibrated internal oscillator this rc oscillator provides an approximate 32 kh z clock. a factory-calibra ted value is written to the 32 khz oscillator calib ration register during rese t to ensure that the os cillator is running within its specification. the calibration register can also be written from software for run-time calibration of the oscillator frequency. the oscillator employs a built in prescaler providing both a 32 khz output and a 1 khz output. 7.4.1.3 32 mhz run-time calib rated internal oscillator this rc oscillator provides an approximate 32 mhz cl ock. the oscillator employs a digital fre- quency looked loop (dfll) that can be enabled for automatic run-time calibration of the oscillator. a factory-calibrated value is written to the 32 mhz dfll calibration register during reset to ensure that the oscillator is running withi n its specification. the calibration register can also be written from software for manual run-time calibration of the oscillator.
70 8077b?avr?06/08 xmega a 7.4.1.4 2 mhz run-time calib rated internal oscillator this rc oscillator provides an approximate 2 mhz clock. the os cillator employs a digital fre- quency looked loop (dfll) that can be enabled for automatic run-time calibration of the oscillator. a factory-calibrated va lue is written to the 2 mhz dfll calibration register during reset to ensure that the oscillator is running withi n its specification. the calibration register can also be written from software for manual run-time calibration of the oscillator. 7.4.2 external clock sources the xtal1 and xtal2 pins can be us ed to drive an external oscilla tor, either a quartz crystal or a ceramic resonator. xtal1 can be used as input for an external clock signal. the tosc1 and tosc2 pins is dedicated for driv ing a 32 khz crystal oscillator. 7.4.2.1 0.4 - 16 mh z crystal oscillator this oscillator can operate in four different modes, optimized for different frequency ranges, all within 0.4 - 16 mhz. figure 7-2 shows a typical connection of a crystal oscillator or resonator. figure 7-2. crystal oscillator connection two capacitors, c1 and c2, may be added to match the required load capacitance for the con- nected crystal. 7.4.2.2 external clock input to drive the device from an external clock source, xtal1 must be driven as shown in figure 7- 3 on page 70 . in this mode, xtal2 can be used as a general i/o pin. figure 7-3. external clock drive configuration 7.4.2.3 32 khz cr ystal oscillator a 32 khz crystal oscillator can be connected between tosc1 and tosc2 by enabling a dedi- cated low frequency oscillator in put circuit. a typical connec tion is shown in figure figure 7-4 c1 c2 xtal2 xtal1 gnd external clock signal nc xtal2 xtal1 gnd
71 8077b?avr?06/08 xmega a on page 71 . a low power mode with reduced voltage swing on tosc2 is available. this oscilla- tor can be used as clock source for the system clock, rtc and the dfll reference. figure 7-4. 32 khz crystal os cillator connection two capacitors, c1 and c2, may be added to match the required load capacitance for the con- nected crystal. 7.5 system clock se lection and prescalers all the calibrated internal oscillators, the pos sible external clock sources (xosc) and the pll output can be used as the system clock source. the system clock source is selectable from software, and can be changed during normal operation. built-in hardware protection prevents unsafe clock switching. it is no t possible to select a non-stable or disabled oscillator as clock source, or to disable the oscilla tor currently used as system cl ock source. each oscillator option has a status flag that can be read from software to check that the oscillator is ready. the system clock is fed into a prescaler block that can divide the clock signal by a factor from 1 to 2048 before it is routed to the cpu and peripherals. the prescaler settings can be changed from software during normal operation. the first stage, prescaler a, can divide by a factor of 1 to 512. then prescaler b and c can be individually configured to either pass the clock through or divide it by a factor of 1 to 4. the prescale r guarantees that derived clocks are always in phase, and that no glitches or intermediate frequencies occur when changing the prescaler setting. the prescaler settings are always updated in accordance to the rising edge of the slowest clock. figure 7-5. system clock selection and prescalers c1 c2 tosc2 tosc1 gnd prescaler a 1, 2, 4, ... , 512 prescaler b 1, 2, 4 prescaler c 1, 2 internal 2 mhz osc. internal 32 khz osc. internal 32 mhz osc. xosc. internal pll clk cpu clk per2 clk per4 clock selection clk per clk sys
72 8077b?avr?06/08 xmega a prescaler a divides the system clock and the resulting clock is the clk per4 . prescaler b and prescaler c can be enabled to di vide the clock speed further and enable peripheral modules to run at twice or four times the cpu clock frequency. if prescaler b and c are not used all the clocks will run at the same frequency as output from prescaler a. the system clock selection and prescaler registers are protected by the configuration change protection mechanism, employing a timed write procedure for changing the system clock and prescaler settings. for details refer to ?configuration change protection? on page 12 . 7.6 pll with 1-31x multiplication factor a built-in phase locked loop (pll) can be used to generate a high frequency system clock. the pll has a user selectable multiplication factor from 1 to 31. the output frequency, f out is given by the input frequency, f in multiplied with the multiplication fa ctor, pll_fac. the pll must have a minimum output frequency of 10 mhz. four different reference clock sources can be chosen as input to the pll: ? 2 mhz internal oscillator ? 32 mhz internal oscillator divided by 4 ? 0.4 - 16 mhz crystal oscillator ? external clock to enable the pll the following procedure must be followed: 1 .enable clock reference source. 2 .set the multiplication factor and select the clock reference for the pll. 3 .wait until the clock reference source is stable. 4 .enable the pll. hardware ensures that the pll configuration cannot be changed when the pll is in use. the pll must be disabled before a new configuration can be written. it is not possible to use the pll before the selected clock source is stabile and the pll has locked. if using pll and dfll the active reference cannot be disabled. 7.7 dfll 2 mhz and dfll 32 mhz two built-in digital frequency locked loops (dflls ) can be used to improve the accuracy of the 2 mhz and 32 mhz internal oscillators. the dfll compares the oscillator frequency with a more accurate refere nce clock to do automatic run-time calibration of th e oscillator. the choices for the reference clock sources are: f out f in pll_fac ? =
73 8077b?avr?06/08 xmega a ? 32 khz calibrated internal oscillator ? 32 khz crystal oscillator co nnected to the tosc pins the dflls divide the reference clock by 32 to us e a 1khz reference. the reference clock is indi- vidually selected for each dfll as shown on figure 7-6 on page 73 . figure 7-6. figure 5-5. dfll reference clock selection when the dfll is enable d it will count each oscillator clock cycle, and for each reference clock edge, the counter value is compared to the fix ed ideal relationship between the reference clock and the 1khz refer ence frequency. if the inter nal oscillator runs too fa st or too slow, the dfll will decrement or increment the co rresponding dfll calibration re gister value by one to adjust the oscillator frequency slightly. when the df ll is enabled the dfll calibration register can- not be written from software. the ideal counter value representing the number of oscillator clock cycles for each reference clock cycle is loaded to the dfll oscillator comp are register during rese t. the register can also be written from software to change the freq uency the internal osc illator is calibrated to. the dfll will stop when entering a sleep-mode w here the oscillators are stopped. after wake- up the dfll will continue with the calibration value found befo re entering sleep. for the dfll calibration register to be reloaded with the default value it has after reset, the dfll must dis- abled before entering sleep and enabled the again after leaving sleep. the active reference cannot be disabled when the dfll is enabled. when the dfll is disabled the dfll calibration register can be written from software for man- ual run-time calibrati on of the oscillator. for details on internal oscillator accuracy when the dfll is enabled, refer to the device data sheet. tosc1 tosc2 32 khz crystal osc. 32 khz int. osc. 2 mhz int. osc. 32 mhz int. osc. dfll dfll
74 8077b?avr?06/08 xmega a 7.8 external clock source failure monitor to handle external clock source failures, there is a built-in moni tor circuit monitoring the oscilla- tor or clock used to derive the xosc clock. the external clock source failure monitor is disabled by default, and it must be enabled from software before it can be used. if an external clock or oscillator is used to derive the system clock (i.e clock reference for the pll when this is used as the active system clock) and an cl ock or oscillator fails (stops), the device will: ? switch to the 2 mhz internal oscillator, in dependently of any clock system lock setting. ? reset the oscillator control re gister and system clock select ion register to their default values. ? set the external clock source failure detection interrupt flag. ? issue a non-maskable interrupt (nmi). if the external oscillator fails wh en it is not used as the system clock source, the external oscil- lator is automatically disabl ed while the system clock will co ntinue to op erate normally. if the external clock is below 32 khz then the failure monitor mechanism should not be enabled in order to avoid unintentional fail detection. when the failure monitor is enabled, it cannot be disabled until next reset. the failure monitor is automatically disabled in all sleep modes where the external clock or oscil- lator is stopped. during wake-up from sleep it is automatically enabled again. the external clock source failure monitor setting is protected by the configuration change pro- tection mechanism, employing a timed write procedure for changing the system clock and prescaler settings. for details refer to see ?modes of cpu change protection? on page 13.
75 8077b?avr?06/08 xmega a 7.9 register descr iption - clock 7.9.1 ctrl - system clock control register ? bit 7:3 - res: reserved these bits are unus ed and reserved for future use. for compatibility with futu re devices, always write these bits to zero when this register is written. ? bit 2:0 - sclksel[2:0]: system clock selection sclksel is used to select the so urce for the system clock. see table 7-1 for the different selections. changing the system clock source wi ll take 2 clock cycles on the old clock source and 2 clock cycles on the new clock source. t hese bits are protected by the configuration change protection mechanism, for details refer to ?configuration change protection? on page 12 . sclksel cannot be changed if the new source is not stable. 7.9.2 psctrl - system clock prescaler register ? bit 7 - res: reserved this bit is reserved and will a lways be read as zero. for compat ibility with future devices, always write this bit to zero when this register is written. bit 76543210 +0x00 ----- sclksel[2:0] ctrl read/writerrrrrr/wr/wr/w initial value00000000 table 7-1. system clock selection sclksel[2:0] group configuration description 000 rc2mhz 2 mhz internal rc oscillator 001 rc32mhz 32 mhz internal rc oscillator 010 rc32khz 32 khz internal rc oscillator 011 xosc external oscillator or clock 100 pll phase locked loop 101 - reserved 110 - reserved 111 - reserved bit 76543210 +0x01 - psadiv[4:0] psbcdiv psctrl read/write r r/w r/w r/w r/w r/w r/w r/w initial value00000000
76 8077b?avr?06/08 xmega a ? bit 6:2 - psadiv[4:0]: prescaler a division factor these bits define the division ratio of the clock prescaler a according to table 7-2 . these bits can be written run-time to change the clock frequency of the clk per4 clock relative to the system clock, clk sys . ? bit 1:0 - psbcdiv: prescaler b and c division factor these bits define the division ratio of the clock prescaler b and c according to table 7-3 . pres- caler b will set the clock frequency for the clk per2 clock relative to the clk per4 . prescaler c will set the clock frequency for the clk per and clk cpu clocks relative to the clk per2 clock. refer to fig- ure 7-5 on page 71 fore more details. table 7-2. prescaler a division factor psadiv[4:0] group configuration description 00000 1 no division 00001 2 divide by 2 00011 4 divide by 4 00101 8 divide by 8 00111 16 divide by 16 01001 32 divide by 32 01011 64 divide by 64 01101 128 divide by 128 01111 256 divide by 256 10001 512 divide by 512 10101 reserved 10111 reserved 11001 reserved 11011 reserved 11101 reserved 11111 reserved table 7-3. prescaler b and c division factor psbcdiv[1:0] group configuration prescaler b division prescaler c division 00 1_1 no division no division 01 1_2 no division divide by 2 10 4_1 divide by 4 no division 11 2_2 divide by 2 divide by 2
77 8077b?avr?06/08 xmega a 7.9.3 lock - clock system lock register ? bit 7:1 - res: reserved these bits are reserved and will always be read as zero. for compatibility with future devices, always write these bits to zero when this register is written. ? bit 0 - lock: clock system lock when the lock bit is written to one the ctrl and psctrl registers cannot be changed, and the system clock selection and prescaler settings is protected against all further updates until after the next reset. this bits are protected by the configuration change protection mechanism, for details refer to ?configuration change protection? on page 12 . the lock bit will only be cleared by a system reset. 7.9.4 rtcctrl - rt c control register ? bit 7:4 - res: reserved these bits are unus ed and reserved for future use. for compatibility with futu re devices, always write these bits to zero when this register is written. ? bit 3:1 - rtcsrc[2:0]: clock source these bits select the clock source for the real time counter according to table 7-4 . bit 76543210 +0x02 - -- - -- - lock lock read/writerrrrrrrr/w initial value 0 0 0 0 0 0 0 0 bit 76543210 +0x03 ---- rtcsrc[2:0] rtcenrtcctrl read/writerrrrr/wr/wr/wr/w initial value00000000 table 7-4. rtc clock source rtcsrc[2:0] group configuration description 000 ulp 1 khz from internal 32 khz ulp 001 tosc 1 khz from 32 khz crystal oscillator on tosc 010 rcosc 1 khz from internal 32 khz rc oscillator 011 - reserved 100 - reserved 101 tosc32 32 khz from 32 khz crystal oscillator on tosc 110 - reserved 111 - reserved
78 8077b?avr?06/08 xmega a ? bit 0 - rtcen: rtc clock source enable setting the rtcen bit will enable the selected clock source for the real time counter. 7.10 register descr iption - oscillator 7.10.1 ctrl - oscillator control register ? bit 7:5 - res: reserved these bits are unus ed and reserved for future use. for compatibility with futu re devices, always write these bits to zero when this register is written. ? bit 4 - pllen: pll enable setting this bit enables the pll. before the pll is enabled, it should be configured with the desired multiplication factor and input source. see ?status - oscillator status register? on page 79. . ? bit 3 - xoscen: external oscillator enable setting this bit enables the selected external clock source, refer to ?xoscctrl - xosc control register? on page 79 for details on how to select and enable an external clock source. the external clock source should be allowed time to become stable before it is selected as source for the system clock. see ?status - oscillator status register? on page 79. ? bit 2 - rc32ken: 32 khz internal rc oscillator enable setting this bit enables the 32 khz internal rc osc illator. the oscilla tor must be stab le before it is selected as source for the system clock. see ?status - oscillator status register? on page 79. ? bit 1- rc32men: 32 mhz internal rc oscillator enable setting this bit will enable the 32 mhz internal rc oscillator. the oscillato rs should be allowed time to become stable before wither is selected as source for the system clock. see ?status - oscillator status register? on page 79. ? bit 0 - rc2men: 2 mhz internal rc oscillator enable setting this bit enables the 2mhz internal rc oscillator. the osc illator should be allowed time to become stable before wither is selected as source for the system clock. see ?status - oscil- lator status register? on page 79. by default the 2 mhz internal rc oscilla tor is enabled and this bit is set. bit 76543210 +0x00 - - - pllen xoscen rc32ken rc32men rc2men ctrl read/write r r r r/w r/w r/w r/w r/w initial value00000001
79 8077b?avr?06/08 xmega a 7.10.2 status - oscillator status register ? bit 7:5 - res: reserved these bits are reserved and will always be read as zero. for compatibility with future devices, always write these bits to zero when this register is written. ? bit 4 - pllrdy: pll ready the pllrdy flag is set when the pll has lo cked on selected frequency and ready to be used as he system clock source. ? bit 3 - xoscrdy: external clock source ready the xoscrdy flag is set when the external clock source is stable and ready to be used as the system clock source. ? bit 2 - rc32krdy: 32 khz internal rc oscillator ready the rc32krdy flag is set when the 32 khz internal rc oscillator is stable and ready to be used as the system clock source. ? bit 1 - rc32mrdy: 32 mhz internal rc oscillator ready the r32mrfy flag is set when the 32 mhz inter nal rc oscillator is stable and ready to be used as the system clock source. ? bit 0 - rc2mrdy: 2 mhz internal rc oscillator ready the rc2mrdy flag is set when t he 2 mhz internal rc oscillato r is stable and is ready to be used as the system clock source. 7.10.3 xoscctrl - xo sc control register ? bit 7:6 - frqrange[1:0]: crystal oscillator frequency range select these bits select the frequen cy range for the connected cr ystal oscillator according to table 7-5 on page 80 . bit 765 4 3 2 1 0 +0x01 - - - pllrdy xoscrdy rc32krdy r32mrdy rc2mrdy status read/write r r r r r r r r initial value 0 0 0 0 0 0 0 0 bit 7 6 5 43210 +0x02 frqrange[1:0] x32klpm - xoscsel[3:0] xoscctrl read/write r/w r/w r/w r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0
80 8077b?avr?06/08 xmega a ? bit 5 - x32klpm: crystal oscillator 32 khz low power mode setting this bit enables low power mode for the 32 khz crystal oscillator. this will reduce the swing on the tosc2 pin. ? bit 4 - res: reserved this bit is reserved and will a lways be read as zero. for compat ibility with future devices, always write this bit to zero when this register is written. ? bit 3:0 - xoscsel[3:0]: crystal oscillator selection these bits select the type and start-up time for the crystal or resonator that is connected to the xtal pins. it is impossible to change this conf iguration when xoscen in ctrl is set. see table 7-6 for crystal selections.. notes: 1. this option should only be used when frequ ency stability at start-up is not important for the application. the option is not suitable for crystals. 2. this option is intended for use with cerami c resonators and will ensure frequency stability at start-up. it can also be used when the frequen cy stability at start-up is not important for the application. 7.10.4 xoscfail - xosc failure detection register table 7-5. oscillator frequency range selection frqrange[1:0] group config uration frequency range recommended range for capacitors c1 and c2 (pf) 00 04to2 0.4 mhz - 2 mhz 100 01 2to9 2 mhz - 9 mhz 15 10 9to12 9 mhz - 12 mhz 15 11 12to16 12 mhz - 16 mhz 10 table 7-6. external oscillator selection and startup time xoscsel[3:0] group configuration selected clock source start-up time 0000 extclk external clock 6 clk 0010 32khz 32 khz tosc 16k clk 0011 xtal_256clk (1) 0.4 - 16 mhz xtal 256 clk 0111 xtal_1kclk (2) 0.4 - 16 mhz xtal 1k clk 1011 xtal_16kclk 0.4 - 16 mhz xtal 16k clk bit 765432 1 0 +0x03 ------xoscfdifxoscfdenxoscfail read/writerrrrrrr/wr/w initial value000000 0 0
81 8077b?avr?06/08 xmega a ? bit 7:2 - res: reserved these bits are reserved and will always be read as zero. for compatibility with future devices, always write these bits to zero when this register is written. ? bit 1 - xoscfdif: failure detection interrupt flag if the external clock source oscillator failure monitor is enabled, the xoscfdif is set when a failure is detected. writing logic one to this lo cation will clear xoscfdif. note that having this flag set will not stop the fail monitor circuit to req uest a new interrupt if th e external clock sources are re-enabled and a new failure occurs. ? bit 0 - xoscfden: failure detection enable setting this bit will enable the failure detection monitor, and a non-maskable interrupt will be issued when the xoscfdif is set. this bit is protected by the configuratio n change protection mechanism, refer to ?configuration change protection? on page 12 for details. once enabled, the failure detection will only be dis- abled by a reset. 7.10.5 rc32kcal - 32 khz oscillator calibration register ? bit 7:0 - rc32kcal[7:0]: 32 khz internal oscillator calibration register this register is used to calibrate the internal 32 khz rc oscillator. a factory-calibrated value is loaded from the signature row of the device and written to this register during reset, giving an oscillator frequency of appr oximate 32 khz. the register can also be written from software to cal- ibrate the oscillator frequen cy during normal operation. 7.10.6 pllctrl - pll control register ? bit 7:6 - pllsrc[1:0]: clock source the pllsrc bits select the input source for the pll according to table 7-7 on page 82 . bit 76543210 +0x04 rc32kcal[7:0] rc32kcal read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 +0x05 pllsrc[1:0] - pllfac[4:0] pllctrl read/write r/w r/w r r/w r/w r/w r/w r/w initial value00000000
82 8077b?avr?06/08 xmega a notes: 1. 32 khz tosc cannot be selected as source for the pll. an external clock must be minimum 0.4 mhz to be used as source clock. ? bit 5 - res: reserved this bit is reserved and will a lways be read as zero. for compat ibility with future devices, always write this bit to zero when this register is written. ? bit 4:0 - pllfac[4:0]: multiplication factor the pllfac bits set the multiplication factor for the pll. the multiplication factor can be in the range from 1x to 31x. the output frequency from the pll should not exceed 200 mhz. the pll must have a minimum output frequency of 10 mhz. 7.10.7 dfllctrl - dfll control register ? bit 7:2 - res: reserved these bits are reserved and will always be read as zero. for compatibility with future devices, always write these bits to zero when this register is written. ? bit 1 - rc32mcref: 32 mhz calibration reference this bit is used to select the calibration source for the 32 mhz dfll. by default this bit is zero and the 32 khz internal rc oscillato r is selected. if this bit is se t to one the 32 khz crystal oscil- lator on tosc is selected as reference. ? bit 0 - rc2mcref: 2 mhz calibration reference this bit is used to select the calibration source for the 2 mhz dfll. by default this bit is zero and the 32 khz internal rc os cillator is selected. if this bit is se t to one the 32 khz crystal oscillator on tosc is selected as reference. table 7-7. pll clock source clksrc[1:0] group configuration pll input source 00 rc2m 2 mhz internal rc oscillator 01 - reserved 10 rc32m 32 mhz internal rc oscillator 11 xosc external clock source (1) bit 765432 1 0 +0x06 - - - - - - r32mcref rc2mcref dfllctrl read/write r r r r r r r/w r/w initial value 0 0 0 0 0 0 0 0
83 8077b?avr?06/08 xmega a 7.11 register descrip tion - dfll32m/dfll2m 7.11.1 comp0 - oscillator compare register 0 comp0, comp1 and comp2 represent the register value comp that hold the oscillator com- pare value. during reset comp is loaded with the default value representing the ideal relationship between osc illator frequency and the 1 khz reference clock. ? bit 7:0 - comp[7:0] these bits are the low byte of the comp register. 7.11.2 comp1 - oscillator compare register 1 ? bit 7:0 - comp[15:8] these bits are the middle byte of the comp register. 7.11.3 comp2 - oscillator compare register 2 ? bit 7:4 - res: reserved these bits are reserved and will always be read as zero. for compatibility with future devices, always write these bits to zero when this register is written. ? bit 3:0 - comp[19:16] these bits are the highest bits of the comp register. 7.11.4 cala - calibration register a cala and calb register holds the 11 bit dfll calibration value that is used for automatic run- time calibration the internal oscillator. when the dfll is disabled, the calibration registers can be written by software for manual ru n-time calibration of the oscillator. bit 76543210 +0x04 comp[7:0] comp0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 +0x05 comp[15:8] comp1 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 +0x06 ----- comp[19:16] comp2 read/write r r r r r r/w r/w r/w initial value 0 0 0 0 0 0 0 0
84 8077b?avr?06/08 xmega a ? bit 7:0 - call[6:0]: dfll calibration bits these bits hold the 7 least significant bits (lsb) of the calibration value for the oscillator. the bits are controlled by the dfll when the dfll is enabled. 7.11.5 calb - calibration register b ? bit 7:5 - res: reserved these bits are reserved and will always be read as zero. for compatibility with future devices, always write these bits to zero when this register is written. ? bit 4:0 - calh[11:7]: dfll calibration bits these bits hold the 5 most signif icant bits (msb) of th e calibration value for the oscillator. a fac- tory-calibrated value is loaded from the signature row of the device and written to this register during reset, giving an oscilla tor frequency approximate to the nominal freq uency for the oscillator. 7.11.6 ctrl - dfll control register ? bit 7:1 - res: reserved these bits are reserved and will always be read as zero. for compatibility with future devices, always write these bits to zero when this register is written. ? bit 0 - enable: dfll enable setting this bit enables the dfll and auto -calibration of the internal oscillator. bit 76543210 +0x02 call[6:0] cala read/write r r r r/w r/w r/w r/w r/w initial value00000000 bit 76543210 +0x03 - - - calh[11:7] calb read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 x x x x x bit 76543210 +0x00 -------e nable ctrl read/writerrrrrrrr/w initial value00000000
85 8077b?avr?06/08 xmega a 7.12 register summary 7.12.1 clock 7.12.2 oscillator 7.12.3 dfll32m/dfll2m address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page +0x00 ctrl - - - - - sclksel[2:0] 75 +0x01 psctrl - psadiv[4:0] psbcdiv[1:0] 75 +0x02 lock - - - - - - - lock 77 +0x03 rtcctrl - - - - rtcsrc[2:0] rtcen 77 +0x04 reserved - - - - - - - - +0x05 reserved - - - - - - - - +0x06 reserved - - - - - - - - +0x07 reserved - - - - - - - - address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page +0x00 ctrl - - - pllen xoscen rc32ken r32men rc2men 78 +0x01 status - - - pllrdy xoscrdy rc32krdy r32mrdy rc2mrdy 78 +0x02 xoscctrl frqrange[1:0] x32klpm - xoscsel[3:0] 79 +0x03 xoscfail - - - - - - xoscfdif xoscfden 80 +0x04 rc32kcal rc32kcal[7:0] 81 +0x05 pllctrl pllsrc[1:0] - pllfac[4:0] 81 +0x06 dfllctrl - - - - - - r32mcref rc2mcref 82 +0x07 reserved - - - - - - - - +0x08 reserved - - - - - - - - +0x09 reserved - - - - - - - - +0x0a reserved - - - - - - - - +0x0b reserved - - - - - - - - +0x0c reserved - - - - - - - - +0x0d reserved - - - - - - - - +0x0e reserved - - - - - - - - +0x0f reserved - - - - - - - - address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page +0x00 ctrl enable 84 +0x01 reserved - ------ - +0x02 cala call[6:0] 83 +0x03 calb - - - calh[11:7] 84 +0x04 comp0 comp[7:0] 83 +0x05 comp1 comp[15:8] 83 +0x06 comp2 - - - - comp[19:16] 83 +0x07 reserved - - - - - - - -
86 8077b?avr?06/08 xmega a 8. power management and sleep 8.1 features ? 5 sleep modes ?idle ? power-down ?power-save ?standby ? extended standby ? power reduction register to disa ble clock to unused peripherals 8.2 overview xmega provides various sleep modes and software controlled clock gating in order to tailor power consumption to the application's requirement. sleep modes enables the microcontroller to shut down unused modules to save power. when the device enters sleep mode, program exe- cution is stopped and interrupts or reset is used to wake the device again. the individual clock to unused peripherals can be stopped during normal oper ation or in sleep, enabling a much more fine tuned power management than sleep modes alone. 8.3 sleep modes sleep modes are used to shut down modules and clock domains in the microcontroller in order to save power. xmega ha s five different sleep modes. a de dicated sleep instruction (sleep) is available to enter sleep. before executing sleep, sleep must be enabled with a selected sleep mode. the available interrupt wake-up sources is dependent on the selected sleep mode. when an enabled interrupt occurs the device will wa ke up and execute the in terrupt service routine before continuing normal program execution from the first instruction after the sleep instruc- tion. if other higher priority interrupts are pending when the wake-up occurs, their interrupt service routines will be executed a ccording to their priority before the interrupt serv ice routine for the wake-up interrupt is executed . after wake-up th e cpu is halted for four cycles before execu- tion starts.
87 8077b?avr?06/08 xmega a table 8-1 on page 87 shows the different sleep modes and the active clock domains, oscillators and wake-up sources. the wake-up time for the device is dependent on the sleep mode and the main clock source. the start-up time for the system clock source must be added to the wake-up time for sleep modes where the clock source is stopped. for deta ils on the start-up time for the different oscil- lators options refer to section 7. ?system clock and clock options? on page 67 . the content of the register file, sram and registers are kept during sleep. if a reset occurs during sleep, the device will reset, star t up and execute from the reset vector. 8.3.1 idle mode in idle mode the cpu and non-volatile memory are stopped, (note that any active programming will be completed) but all peripherals including the interrupt controller, event system and dma controller are kept running. any interrupt request interr upts will wake the device. 8.3.2 power-down mode in power-down mode all system clock sources, including the real time counter clock source are stopped. this allows operation of asynchronous modules only. the only interrupts that can wake up the mcu are the two wire interface address match interrupts, and asynchronous port interrupts. 8.3.3 power-save mode power-save mode is identical to power-down, with one exception: if the real time counter (rtc) is enabled, it will keep running during sl eep and the device can also wake up from either rtc overflow or compare match interrupt. table 8-1. active clock domains an d wake-up sources in the different sleep modes. active clock domain oscillators wake-up sources sleep modes cpu clock peripheral clock rtc clock system clock source rtc clock source asynchronous port interrupts twi address match interrupts real time clock interrupts all interrupts idle x x x x xxxx power-down x x power-save x x x x x standby x x x extended standby x x x x x x
88 8077b?avr?06/08 xmega a 8.3.4 standby mode standby mode is identical to power-down with t he exception that the system clock sources are kept running, while the cpu, peripheral and rtc clocks are stopped. this reduces the wake-up time. 8.3.5 extended standby mode extended standby mode is identical to power-save mode with the exception that the system clock sources are kept running while the cpu and peripheral clocks are stopped. this reduces the wake-up time. 8.4 power reduction registers the power reduction registers (prr) provides a me thod to stop the clock to individual periph- erals. when this is done the current state of the peripheral is frozen and the associated i/o registers cannot be r ead or written. resource s used by the peripheral will remain occupied; hence the peripheral should in most cases be disabled before stopping the clock. enabling the clock to a peripheral again, puts the peripheral in the same state as before it was stopped. this can be used in idle mode and active mode to reduce the overall power consumption signifi- cantly. in all other sleep modes, the peripheral clock is already stopped. not all devices have all the peripherals associated with a bit in the power reduction registers. setting a prr bit for a peripheral that is not available will have no effect. 8.5 register description ? sleep 8.5.1 ctrl- sleep control register ? bit 7:4 - res: reserved these bits are unus ed and reserved for future use. for compatibility with futu re devices, always write these bits to zero when this register is written. ? bit 3:1 - smode[2:0]: sleep mode these bits select sleep modes according to table 8-2 on page 89 . bit 76543210 +0x00 ---- smode[2:0] senctrl read/writerrrrr/wr/wr/wr/w initial value00000000
89 8077b?avr?06/08 xmega a table 8-2. sleep mode ? bit 1 - sen: sleep enable this bit must be set to make the mcu enter the selected sleep mode when the sleep instruc- tion is executed. to avoid unintentional entering of sleep modes, it is recommended to write sen just before executing the sl eep instruction, and clearing it immediately after waking up. 8.6 register description ? power reduction registers 8.6.1 pr - general power reduction register ? bit 7:5 - res: reserved these bits are reserved and will always be read as zero. for compatibility with future devices, always write these bits to zero when this register is written. ? bit 4 - aes: aes module setting this bit stops the clock to the aes module . when the bit is clea red the peripheral should be reinitialized to ensure proper operation. ? bit 3 - ebi: external bus interface setting this bit stops the clock to the external bu s interface. when the bit is cleared the periph- eral should be reinitialized to ensure proper operation. note that the ebi is not present for all devices. ? bit 2 - rtc: real-time counter setting this stops the clock to the real time counter. when the bit is cleared the peripheral should be reinitialized to ensure proper operation. smode[2:0] sen group c onfiguration description xxx 0 off no sleep mode enabled 000 1 idle idle mode 001 1 - reserved 010 1 pdown power-down mode 011 1 psave power-save mode 100 1 - reserved 101 1 - reserved 110 1 stdby standby mode 111 1 estdby extended standby mode bit 76543210 +0x00 - - - aes ebi rtc evsys dmac pr read/write r r r r/w r/w r/w r/w r/w initial value00000000
90 8077b?avr?06/08 xmega a ? bit 1 - evsys: event system setting this stops the clock to t he event system. when the bit is cleared the module will continue like before the shutdown. ? bit 0 - dmac: dma-controller setting this stops the clock to the dma controller. this bit can only be set if the dma controller is disabled. 8.6.2 prpa/b - power redu ction port a/b register note: disabling of analog modules stops the clock to the analog blocks themselves and not only the interfaces. ? bit 7:3 - res: reserved these bits are reserved and will always be read as zero. for compatibility with future devices, always write these bits to zero when this register is written. ? bit 2 - dac: power reduction dac setting this bit stops the clock to the dac. the dac should be disabled before shut down. ? bit 1 - adc: power reduction adc setting this bit stops the clock to the adc. the adc should be disabled before shut down. ? bit 0 - ac: power reduction analog comparator setting this bit stops the clock to the analog comparator. the ac should be disabled before shut down. 8.6.3 prpc/d/e/f - power reduction port c/d/e/f register ? bit 7 - res: reserved this bit is reserved and will a lways be read as zero. for compat ibility with future devices, always write this bit to zero when this register is written. ? bit 6 - twi: two-wire interface setting this bit stops the clock to the two-wire interface. when the bit is cleared the peripheral should be reinitialized to ensure proper operation. bit 765432 1 0 +0x01/+0x02 -----dacadcacprpa/b read/writerrrrrr/wr/wr/w initial value000000 0 0 bit 76543210 - twi usart1 usart0 spi hires tc1 tc0 prpc/d/e/f read/write r r/w r/w r/w r/w r/w r/w r/w initial value00000000
91 8077b?avr?06/08 xmega a ?bit 5 - usart1 setting this bit stops the clock to the usart1. w hen the bit is cleared the peripheral should be reinitialized to ensure proper operation. ?bit 4 - usart0 setting this bit stops the clock to the usart0. w hen the bit is cleared the peripheral should be reinitialized to ensure proper operation. ? bit 3 - spi: serial peripheral interface setting this bit stops the clock to the spi. when the bit is cleared the peripheral should be reini- tialized to ensure proper operation. ? bit 2 - hires: hi-resolution extension setting this bit stops the clock to the hi-resolution extension for the timer/counters. when the bit is cleared the peripheral should be reinitialized to ensure proper operation. ? bit 1 - tc1: timer/counter 1 setting this bit stops the clock to the timer/coun ter 1. when the bit is cleared the peripheral will continue like before the shut down. ? bit 0 - tc0: timer/counter 0 setting this bit stops the clock to the timer/coun ter 0. when the bit is cleared the peripheral will continue like before the shut down.
92 8077b?avr?06/08 xmega a 8.7 register summary 8.7.1 sleep 8.7.2 power reduction registers address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page +0x00 ctrl smode[2:0] sen 88 +0x01 reserved - - - - - - - - +0x02 reserved - - - - - - - - +0x03 reserved - - - - - - - - +0x04 reserved - - - - - - - - +0x05 reserved - - - - - - - - +0x06 reserved - - - - - - - - +0x07 reserved - - - - - - - - address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page +0x00 pr - - - aes ebi rtc evsys dmac 89 +0x01 prpa - - - - - dac adc ac 90 +0x02 prpb - - - - - dac adc ac 90 +0x03 prpc - twi usart1 usa rt0 spi hires tc1 tc0 90 +0x04 prrd - twi usart1 usart0 spi hires tc1 tc0 90 +0x05 prre - twi usart1 usart0 spi hires tc1 tc0 90 +0x06 prrf - twi usart1 usart0 spi hires tc1 tc0 90 +0x07 reserved - - - - - - - -
93 8077b?avr?06/08 xmega a 9. system control and reset 9.1 features ? power-on reset source ? brown-out reset source ? spike detection reset source ? software reset source ? external reset source ? watchdog reset source ? program and debug interface reset source 9.2 overview the reset system will issue a system reset and set t he device to its initial state if a reset source goes active. all io registers will be set to their initial value, and the program counter is reset to the reset vector location. the reset controller is asynchronous, hence no running clock is required to reset the device. xmega has seven different reset sources. if mo re than one reset source is active, the device will be kept in reset until all rese t sources have released their re set. after reset is released from all reset sources, the default oscillator is started and calibrated before the internal reset is released and the device starts running. the reset system has a status register with indi vidual flags for each re set source. the status register is cleared at power-on reset, hence this register will show which source(s) that has issued a reset since the last power-on. a software reset feature makes it possible to issue a sys- tem reset from the user software. an overview of the reset system is shown in figure 9-1 on page 94 .
94 8077b?avr?06/08 xmega a figure 9-1. reset system overview reset delay counter oscillator startup oscillator calibration power - on detection reset spike detection reset brown - out detection reset external reset watchdog reset program and debug interface reset software reset r s reset status register internal reset timeout counter reset
95 8077b?avr?06/08 xmega a 9.3 reset sequence reset request from any reset source immediately reset the device, and keep it in reset as long as the request is active. when all reset requests are released, the device will go through three stages before the internal reset is released and the device starts running. ? reset counter delay ? oscillator startup ? oscillator calibration if one of the reset request occu r during this, the reset sequence will start from the beginning. 9.3.1 reset counter delay the reset counter delay is the programmable period from all reset requests are released and until the reset counter times out and releases reset. the reset counter delay is timed from the 1 khz output of the ultra low power (ulp) internal oscillator, and the number of cycles before the timeout is set by the startuptime fuse bits. the selectable delays are shown in table 9- 1 . 9.3.2 oscillator startup after the reset counter delay, the default clock is started. this is the 2 mhz internal rc oscilla- tor, and this uses 6 clock cycles to startup and stabilize. 9.3.3 oscillator calibration after the default oscillator has st abilized, oscillator calibration va lues are loaded from non-vola- tile memory into the oscillator calibration registers. loading the calibration values takes 24 clock cycles on the internal 2 mh z oscillator. the 2 mhz, 32 mh z and 32 khz internal rc oscil- lators are calibrated. when this is done the device will enter active state. 9.4 reset sources 9.4.1 power-on reset a power-on detection circuit will give a po wer-on reset (por) w hen supply voltage (v cc ) is applied to the device and the v cc slope is increasing in the power-on slope range (v posr ). power-on reset is released when the v cc stops rising or when the v cc level has reached the power-on threshold voltage (v pot ) level. when v cc is falling, the por will issue a reset when th e vpot level is reach ed. the vpot level is lower than the minimum operating voltage for the device, and is only used for power-off function- table 9-1. reset counter delay sut[1:0] 1khz ulp oscillator clock cycles 00 64 01 4 10 reserved 11 0
96 8077b?avr?06/08 xmega a ality and not to ensure safe operation. the brown-out detection (bod) must be enabled to ensure safe operation and detect if v cc voltage drops below minimum operating voltage. only the power-on reset flag w ill be set after power-on reset. the brown-out reset flag is not set even though the bod circuit is used. figure 9-2. power-on reset (por). figure 9-3. increasing v cc slope in the power-on slope range. for characterization data on the v pot level for rising and falling v cc , and v posr slope consult the device data sheet. note that the power-on detection circuit is not designed to detect drops in the v cc voltage. brown-out detection must be enabled to detect falling v cc voltage, even if the v cc level falls below the v pot level. cc v timeout i n ter n al reset t tout v bot v pot v t v pot v posr,max v cc v cc dv dt
97 8077b?avr?06/08 xmega a 9.4.2 brown-out detection the brown-out detection (bod) circuit monitors that the v cc level is kept above a configurable trigger level, v bot . when the bod is enabled, a bod reset will be given if the v cc level falls bel- low the trigger level for a minimum time, t bod . the reset is kept active until the v cc level rises above the trigger level again. the trigger level has a hysteresis that ensures spike free operation. figure 9-4. brown-out detection reset. for characterization data on t bod consult the device data sheet. the trigger level is determined by the bodlevel fuse setting, see table 9-2 . note: 1. the values here are nominal values only. for typical, maximum and minimum numbers consult the device data sheet. the bod circuit has 3 modes of operation: ? disabled: in this mode there is no monitoring of the v cc level, and hence it is only recommended for applications where the power supply is stable. ? enabled: in this mode the v cc level is continuously monitored, and a drop in v cc below v bot for at least t bod will give a brown-out reset. table 9-2. bodlevel fuse coding bodlevel[2:0] (1) v bot unit 111 1.6 v 110 1.8 101 2.0 100 2.2 011 2.4 010 2.7 001 2.9 000 3.2 v cc time-out internal reset v bot- v bot+ t tout t bod
98 8077b?avr?06/08 xmega a ? sampled: in this mode the bod circuit will sample the vcc level with a period identical to the 1 khz output from the ultra low power (ulp) oscillator. between each sample the bod is turned off. this mode will reduce the power co nsumption compared to the enabled mode, but a fall in the v cc level between 2 positive edges of the 1 khz ulp output will not be detected. if a brown-out is detected in this mode, the bod circuit is set in enabled mode to ensure that the device is kept in reset until v cc is above v bot again. the bodact fuse determines the bod setting for active mode and idle mode, while the bodds fuse determines the brown-out detection setting for all sleep modes except idle mode. 9.4.3 spike detector reset the spike detection (sd) circuit is able to detect negative spikes on v cc . when enabled the spike detection circuit will continuously monitor the v cc level and give a reset if there is a nega- tive spike on the v cc level. for a spike to be detected, the v cc fall must be significant and last for longer than a minimum time. the voltage drop, v drop , and the minimum time, t sd , is dependent on each other. a large voltage drop requires a shorter minimum time to generate a reset and vice versa. this implies that a negative spike on v cc may create a reset even though the v cc level is still within the specified operating voltage for the device. figure 9-5. spike detection reset. note: spike detector is always enabled during programming, independent on fuse settings. for characterization data on v drop and t sd consult the device data sheet. table 9-3. bod setting fuse decoding bodact[1:0]/ bodds[1:0] mode 00 reserved 01 sampled 10 enabled 11 disabled v cc time-out internal reset t tout t sd v drop
99 8077b?avr?06/08 xmega a the dvsdon fuse determines if the spike de tector circuit is enabled or disabled. 9.4.4 external reset the external reset circuit is co nnected to the external reset pin. the external reset will trigger when the reset pin is driven below the reset pin threshold voltage, v rst , for longer than the minimum pulse period t ext . the reset will be held as long as the pin is kept low. the reset pin includes an internal pull-up resistor, and a spike filter to suppress noise. figure 9-6. external reset characteristics. for characterization data on v rst and t ext and pull-up resistor values consult the device data sheet. 9.4.5 watchdog reset the watchdog timer (wdt) is a system function for monitoring correct program operation. if the wdt is not reset from the software within a pr ogrammable timout period, a watchdog reset will be given. the watchdog reset is active for 1-2 clock cycles on the 2 mhz internal rc oscillator. figure 9-7. watchdog reset. for information on configuration and use of the wdt, refer to the ?wdt ? watchdog timer? on page 102 . table 9-4. spike detector fuse decoding dvsdon mode 1disabled 0 enabled cc t ext 1-2 2mhz cc cycles
100 8077b?avr?06/08 xmega a 9.4.6 software reset the software reset makes it possible to issue a system reset from software by writing to the software reset bit in the reset c ontrol register.the reset will be issued within 1-2 system clock cpu cycles after writing the bit. it is not possible to execute any instruction from a software reset is requested and until it is issued. figure 9-8. software reset 9.4.7 program and debug interface reset the program and debug interface reset contains a separate reset source that is used to reset the device during external programming and debuggin g. this reset source is only accessible from debuggers and programmers. 9.5 register description 9.5.1 status - reset status register ? bit 7 - res: reserved this bit is reserved and will a lways be read as zero. for compat ibility with future devices, always write this bit to zero when this register is written. ? bit 6 - sdrf: spike detection reset flag this flag is set if a spike dete ction reset occurs. the flag will be cleared by a power-on reset or by writing a one to the bit location. ? bit 5 - srf: software reset flag this flag is set if a software re set occurs. the flag will be cleared by a power-on rese t or by writ- ing a one to the bit location. s oftware cc 1-2 2mhz cycle bit 76543210 +0x00 - sdrf srf pdirf wdrf borf extrf porf status read/write r r/w r/w r/w r/w r/w r/w r/w initial value--------
101 8077b?avr?06/08 xmega a ? bit 4 - pdirf: program and debug interface reset flag this flag is set if a programming interface reset occurs. the flag will be cleared by a power-on reset or by writing a one to the bit location. ? bit 3 - wdrf: watchdog reset flag this flag is set if a watchdog reset occurs. the flag will be cleared by a power-on reset or by writing a one to the bit location. ? bit 2 - borf: brown out reset flag this flag is set if a brown out reset occurs. the flag will be cleared by a power-on reset or by writing a one to the bit location. ? bit 1 - extrf: external reset flag this flag is set if an external reset occurs. the fl ag will be cleared by a power-on reset or by writ- ing a one to the bit location. ? bit 0 - porf: power on reset flag this flag is set if a power-on reset occurs. wr iting a one to the flag will clear the bit location. 9.5.2 ctrl - reset control register ? bit 7:1 - res: reserved these bits are unus ed and reserved for future use. for compatibility with futu re devices, always write these bits to zero when this register is written. ? bit 0 - swrst: software reset when this bit is set, a software reset will occur. the bit is cleared when a reset is issued. this bit is protected by the configuration change protection, for details refer to ?configuration change protection? on page 12 . 9.6 register summary bit 76543210 +0x01 -------swrstctrl read/writerrrrrrrr/w initial value00000000 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page +0x00 status - sdrf srf pdi rf wdrf borf extrf porf 100 +0x01ctrl-- ---- -swrst101
102 8077b?avr?06/08 xmega a 10. wdt ? watchdog timer 10.1 features ? 11 selectable timeout period, from 8 ms to 8s ? two operation modes ? standard mode ? window mode ? runs from 1 khz ultra low power clock reference ? configuration lock 10.2 overview the watchdog timer (wdt) is a system function for monitoring correct program operation, mak- ing it possible to recover from error situations, for instance run-away code. the wdt is a timer, configured to a predefined timeout period and is constantly running when enabled. if the wdt is not reset within the timeout peri od, it will issue a system reset. the wdt is reset by executing the wdr (watchdog timer reset) instruction from the application code. the wdt also has a window mode that enables the user to define a time slot where wdt must be reset within. if the wdt is reset too ea rly or too late, a system reset will be issued. the wdt will run in all power modes if enabled. it runs from a cpu independent clock source, and will continue to operate to issue a syst em reset even if th e main clocks fail. the configuration change protection mechanism ensures that the wdt settings cannot be changed by accident. in addition the settings can be locked by a fuse. 10.3 normal mode operation in normal mode operation a single timeout period is set for the wdt. if the wdt is not reset from the application code bef ore the timeout occurs the wdt will i ssue a system reset. there are 11 possible wdt timeout (to wdt ) periods selectable from 8 ms to 8s, and the wdt can be reset at any time during the period. after each reset, a new timeout period is started. the default timeout period is controlled by fuses. norm al mode operation is illustrated in figure 10-1 . figure 10-1. normal mode operation. t [ms] wdt count 510 15 20 25 30 35 to wdt = 16 timely wdt reset to wdt wdt timeout system reset
103 8077b?avr?06/08 xmega a 10.4 window mode operation in window mode operation the wd t uses two different timeout peri ods, a "closed" window time- out period (to wdtw ) and the normal timeout period (to wdt ). the closed window timeout period defines a duration from 8 ms to 8s where the wdt cannot be reset: if the wdt is reset in this period the wdt will issue a system reset. the norma l wdt timeout period, which is also 8 ms to 8s, defines the duration of the "open" period, in which the wdt can (and should) be reset. the open period will always follow the closed period, so the total duration of the timeout period is the sum of the closed window and the open window timeout periods. the default closed window tim- eout period is controlled by fuses. the window mode operatio n is illustrated in figure 10-2 . figure 10-2. window mode operation. 10.5 watchdog timer clock the wdt is clocked from the 1 khz output from the internal 32 khz ultra low power (ulp) oscil- lator. due to the ultra low power design, the osc illator is not very accurate so the exact timeout period may vary from device to device. w hen designing software which uses the wdt, this device-to-device variation must be kept in mind to ensure that the timeout periods used are valid for all devices. for more information on the ulp oscillator accuracy, consult the device data sheet. 10.6 configuration protection and lock the wdt is designed with two security mechanisms to avoid unintentional changes of the wdt settings. the first mechanism is the configuration change protection mechanism, employing a timed write procedure for changing the wdt control registers. in addition, for the new configuration to be written to the control registers, the register?s change enable bit must be written at the same time. the second mechanism is to lock the configurat ion by setting the wdt lock fuse. when this fuse is set, the watchdog time control register can not be changed, hence the wdt can not be dis- abled from software. a fter system reset the wdt will resume at configured operation. when the wdt lock fuse is programmed the window mode timeout period cannot be changed, but the win- dow mode itself can still be enabled or disabled. t [ms] wdt count 510 15 20 25 30 35 to wdtw = 8 to wdt = 8 timely wdt reset closed to wdtw open to wdt early wdt reset system reset
104 8077b?avr?06/08 xmega a 10.7 registers description 10.7.1 ctrl ? watchdog timer control register ? bits 7:6 - res: reserved these bits are unus ed and reserved for future use. for compatibility with futu re devices, always write these bits to zero when this register is written. ? bits 5:2 - per[3:0]: watchdog timeout period these bits determine the watchd og timeout period as a number of 1 khz ulp oscillator cycles. in window mode operation, these bits define the open window period. the different typical time- out periods are found in table 10-1 . the initial values of these bits are set by the watchdog timeout period (wdp) fuses, and will be loaded at power-on. in order to change these bits the cen bit must be written to 1 at the same time. these bits are protected by the configuration change protection mechanism, for detailed description refer to ?configuration change protection? on page 12 . bit 76543210 +0x00 - - per[3:0] enable cen ctrl read/write (unlocked) r r r/wr/wr/wr/wr/wr/w read/write (locked) rrrrrrrr initial value (x = fuse) 0 0xxxxx0 table 10-1. watchdog timeout periods per[3:0] group configuration typical timeout periods 0000 8clk 8 ms 0001 16clk 16 ms 0010 32clk 32 ms 0011 64clk 64 ms 0100 125clk 0.125 s 0101 250clk 0.25 s 0110 500clk 0.5 s 0111 1kclk 1.0 s 1000 2kclk 2.0 s 1001 4kclk 4.0 s 1010 8kclk 8.0 s 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 reserved
105 8077b?avr?06/08 xmega a ? bit 1 - enable: watchdog enable this bit enables the wdt. in order to change this bit the cen bit in ?ctrl ? watchdog timer control register? on page 104 must be written to one at the same time. this bit is protected by the configuration change protection mechanism, for detai led description refer to ?configuration change protection? on page 12 . ? bit 0 - cen: watchdog change enable this bit enables the possibility to change the configuration of the ?ctrl ? watchdog timer con- trol register? on page 104 . when writing a new value to this register, this bit must be written to one at the same time for the changes to take effect. this bit is protected by the configuration change protection mechanism, for detailed description refer to ?configuration change protec- tion? on page 12 . 10.7.2 winctrl ? window mode control register ? bits 7:6 - res: reserved these bits are unus ed and reserved for future use. for compatibility with futu re devices, always write these bits to zero when this register is written. ? bits 5:2 - wper[3:0]: watchdog window mode timeout period these bits determine the closed window period as a number of 1 khz ulp oscillator cycles in window mode operation. the typical different closed window periods are found in table 10-2 . the initial values of these bits are set by the watchdog window timeout period (wdwp) fuses, and will be loaded at power-on. in norm al mode these bits are not in use. in order to change these bits the wcen bit must be written to one at the same time. these bits are protected by the configuration change protection mechanism, for detailed description refer to ?configuration change protection? on page 12 . bit 76543210 +0x01 - - wper[3:0] wen wcen winctrl read/write (unlocked) r r r/w r/w r/w r/w r/w r/w read/write (locked) rrrrrrr/wr/w initial value (x = fuse) 0 0xxxxx0 table 10-2. watchdog closed window periods wper[3:0] group configuration typ ical closed window periods 0000 8clk 8 ms 0001 16clk 16 ms 0010 32clk 32 ms 0011 64clk 64 ms 0100 125clk 0.125 s 0101 250clk 0.25 s
106 8077b?avr?06/08 xmega a ? bit 1 - wen: watchdog window mode enable this bit enables the watchdog window mode. in order to change this bit the wcen bit in ?winctrl ? window mode control register? on page 105 must be written to one at the same time. this bit is protected by the configur ation change protection mechanism, for detailed description refer to ?configuration change protection? on page 12 . ? bit 0 - wcen: watchdog window mode change enable this bit enables the possibility to change the configuration of the ?winctrl ? window mode control register? on page 105 . when writing a new value to this register, this bit must be written to one at the same time for the changes to take effect. this bit is protected by the configuration change protection mechanism, but not protected by the wdt lock fuse. 10.7.3 status ? watchdog status register ? bit 7:1 - res:reserved these bits are reserved and will always be read as zero. for compatibility with future devices, always write these bits to zero when this register is written. ? bit 0 - syncbusy when writing to the ctrl or winctrl registers, the wdt needs to be synchronized to the other clock domains. duri ng synchronization the syncbusy bit will be read as one. this bit is automatically cleared after the syn chronization is finished. synchr onization will only take place when the enable bit for the watchdog timer is set. 0110 500clk 0.5 s 0111 1kclk 1.0 s 1000 2kclk 2.0 s 1001 4kclk 4.0 s 1010 8kclk 8.0 s 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 reserved table 10-2. watchdog closed window periods (continued) wper[3:0] group configuration typ ical closed window periods bit 7654321 0 +0x02 -------syncbusystatus read/write rrrrrrr r initial value 0 0 0 0 0 0 0 0
107 8077b?avr?06/08 xmega a 10.8 register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page +0x00 ctrl - - per[3:0] enable cen 104 +0x01 winctrl - - wper[3:0] wen wcen 105 +0x02 status - - - - - - - syncbusy 106
108 8077b?avr?06/08 xmega a 11. interrupts and programmable mu lti-level interrupt controller 11.1 features ? separate interrupt vector for each interrupt ? short, predictable in terrupt response time ? programmable multi-level interrupt controller ? 3 programmable interrupt levels ? selectable priority scheme within low level interrupts (round-robin or fixed) ? non-maskable interrupts (nmi) ? interrupt vectors can be moved to the start of the boot section. 11.2 overview interrupts signal a change of state in peripherals, and this can be used to alter program execu- tion. peripherals can have one or more interrupts, and all are individually enabled. when the interrupt is enabled and the inte rrupt condition is present this will generate a corr esponding inter- rupt request. all interrupts have a separate interrupt vector address. the programmable multi-level in terrupt controller (pmic) contro ls the handling of interrupt requests, and prioritizing between the different interrupt levels and interrupt priorities. when an interrupt request is acknowledged by the pmic, the program counter is set to point to the inter- rupt vector, and the interrupt handler can be executed. all peripherals can select between three different priority levels for thei r interrupts; low, medium or high. medium level interrupts will interrupt low level interrupt handlers. high level interrupts will interrupt both medium and low level interrupt handler s. within each level, the interrupt prior- ity is decided from the interrupt vector address, where the lowest interrupt vector address has the highest interrupt priority. low level interrupts have an optional round-robin scheduling scheme to ensure that all interrupts are serviced within a certain amount of time. non-maskable interrupts (nmi) are also supported. 11.3 operation interrupts must be globally enabled for any interrupts to be generated. this is done by setting the global interrupt enable bit (i-bit) in the cp u status register. the i-bit will not be cleared when an interrupt is acknowledged. each interrupt level must also be enabled before interrupts with the corresponding level can be generated. when an interrupt is enabled and the interrupt cond ition is present, the pmic will receive the interrupt request. based on the interrupt level and interrupt priority of any ongoing interrupts, the interrupt is either acknowledged or kept pending until it has priority. when the interrupt request is acknowledged, the program counter is updated to point to the interrupt vector. the interrupt vector is normally a jump to the interrupt handler; the software routine that handles the interrupt. after returning from the interrupt handler, program execution continues from where it was before the interrupt occurred. one instruction is always executed before any pending interrupt is served. the pmic status register contains state informat ion that ensures that the pmic returns to the correct interrupt level when the reti (interrupt return) instruction is executed at the end of an interrupt handler. returnin g from an interrupt will return the pmic to the state it had before enter- ing the interrupt. the status register (sre g) is not saved automatically upon an interrupt
109 8077b?avr?06/08 xmega a request. the ret (subroutine return) instructi on cannot be used when returning from the inter- rupt handler routine, as this will not return the pmic to its right state. 11.4 interrupts all interrupts and the reset vector each have a separate program vector address in the program memory space. the lowest address in the program memory space is the reset vector. all inter- rupts are assigned individual control bits for enabling and setting the interrupt level, and this is set in the control registers for each peripheral that can generate interrupts. details on each inter- rupt are described in the peripheral where the interrupt is available. all interrupts have an interrupt flag associated to it. when the interrupt condition is present, the interrupt flag will be set, even if the corresponding interrupt is not enabled. for most interrupts, the interrupt flag is automatically cleared when executing the interrupt vector. writing a logical one to the interrupt flag will also clear the flag. some interrupt fl ags are not clear ed when execut- ing the interrupt vector, and some are cleared automatically when an associated register is accessed (read or written). this is descri bed for each individual interrupt flag. if an interrupt condition occurs while another higher priority interrupt is executing or pending, the interrupt flag will be set and remembered until the interrupt has priority. if an interrupt condition occurs while the corresponding in terrupt is not enabled, the inte rrupt flag will be set and remem- bered until the interrupt is enabled, or the flag is cleared by software. similarly, if one or more interrupt conditions occur while global interrupts are disabled, the corresponding interrupt flag will be set and remembered until global interrupts are enabled. all pending interrupts are then executed according to their order of priority. interrupts can be blocked when executing code from a locked section, e.g. when the boot lock bits are programmed. this feature improves software security, refer to memory programming for details on lock bit settings. interrupts are automatically di sabled for up to 4 cpu clock cycles when the configuration change protection register is written with the correct signature, refer to ?configuration change protection? on page 12 for more details. 11.4.1 nmi ? non-maskable interrupts non-maskable interrupts (nmi) are hardwired. it is not selectable which interrupts represent nmi and which represent regular interrupts. non-maskable interrupts must be enabled before they can be used. refer to the device data sheet for nmi present on each the device. a nmi will be executed regard less of the setting of the i-bit, a nd it will never change the i-bit. no other interrupts can interrupt a nmi interrupt handler. if more than one nmi is requested at the same time, priority is static according to interrupt vector address where lowest address has high- est priority. 11.4.2 interrupt response time the interrupt response time for all the enabled interrupts is five cpu clock cycles minimum. dur- ing these five clock cycles the program counter is pushed on the stack. after five clock cycles, the program vector for the interrupt is executed. the jump to the interrupt handler takes three clock cycles. if an interrupt occurs during execution of a mult i-cycle instruction, this instruction is completed before the interrupt is served. if an interrupt occurs when the device is in sleep mode, the inter-
110 8077b?avr?06/08 xmega a rupt execution response time is increased by fi ve clock cycles. in addition the response time is increased by the start-up time from the selected sleep mode. a return from an interrupt handling routine takes fi ve clock cycles. during these five clock cycles, the program counter is popped from the stack and the stack pointer is incremented. 11.5 interrupt level the interrupt level is independently selected for each interrupt source. for any interrupt request, the pmic also receives the interrupt level for the interrupt. the interrupt levels and their corre- sponding bit values for the interrupt level configuration of all interrupts is shown in table 11-1 . the interrupt level of an interrupt request is compared against the current level and status of the interrupt controller. an interrupt request on higher level will interrupt any ongoing interrupt han- dler from a lower level interrupt. when returning from the higher level interrupt handler, the execution of the lower level interrupt handler will continue. 11.6 interrupt priority within each interrupt level, all interrupts have a priority. when several interrupt requests are pending, the order of which interrupts are acknowledged is decided both by the level and the pri- ority of the interrupt request. interrupts can be organized in a static or dynamic (round-robin) priority scheme. high and medium level interrupts and the nmi will always have static priority. for low level interrupts, static or dynamic priority scheduling can be selected. 11.6.1 static priority interrupt vectors (ivec) are located at fixed addresses. for static priority, the interrupt vector address decides the priority within one interrupt level where the lowest interrupt vector address has the highest priority. refer to the device data sheet for interrupt vector table with the base address for all modules and peripheral s with interrupt. refer to the interrupt vector summary of each module and peripheral in this manual for a list of interrupts and their corresponding offset address within the different modules and peripherals. table 11-1. interrupt level interrupt level configuration group configuration description 00 off interrupt disabled. 01 lo low level interrupt 10 med medium level interrupt 11 hi high level interrupt
111 8077b?avr?06/08 xmega a figure 11-1. static priority. 11.6.2 round-robin scheduling to avoid the possible starvation problem for low level interrupts with static priority, the pmic gives the possibility for round-r obin scheduling for low level inte rrupts. when round-robin sched- uling is enabled, the interrupt vector address for the last acknowledged low level interrupt will have the lowest priority next time one or mo re interrupts from the low level is requested. figure 11-2. round-robin scheduling. ivec 0 : : : ivec x ivec x+1 : : : ivec n lowest priority highest priority lowest address highest address highest priority iv ec 0 : : : iv ec x iv ec x +1 : : : iv ec n iv ec 0 : : : iv ec x iv ec x +1 : : : iv ec n highest priority low est priority iv ec x +2 ivec x+1 last acknow ledged interrupt low est priority ivec x last acknow ledged interrupt
112 8077b?avr?06/08 xmega a 11.7 moving interrupts between a pplication and boot section the interrupt vectors can be moved from the default location in the application section in flash to the start of the boot section. 11.8 register description 11.8.1 status - pmic status register ? bit 7 - nmiex: non-maskable interrupt executing this flag is set if a non-maskable interrupt is executing. the flag will be cleared when returning (reti) from the interrupt handler. ? bit 6:3 - res: reserved these bits are reserved and will always be read as zero. for compatibility with future devices, always write these bits to zero when this register is written. ? bit 2 - hilvlex: high level interrupt executing this flag is set if a high level interrupt is executing or the interrupt handler has been interrupted by an nmi. the flag will be cleared when return ing (reti) from th e interrup t handler. ? bit 1 - medlvlex: medium level interrupt executing this flag is set if a medium level interrupt is executing or the interrupt handler has been inter- rupted by an interrupt from highe r level or an nmi. the flag will be cleared when returning (reti) from the interrupt handler. ? bit 0 - lolvlex: low level interrupt executing this flag is set if a low level in terrupt is executing or the interrupt handler has been interrupted by an interrupt from higher level or an nmi. the flag will be cleared when returning (r eti) from the interrupt handler. 11.8.2 intpri - pmic priority register ? bit 7:0 - intpri: interrupt priority when round-robin scheduling is enabled, this register stores the interrupt vector of the last acknowledged low-level interrupt. the stored interrupt vector will have the lowest priority next time one or more low-level interrupts are pending. the register is accessible from software to bit 765432 1 0 +0x00 nmiex - - - - hilvlex medlvlex lolvlex status read/write rrrrrr r r initial value 0 0 0 0 0 0 0 0 bit 76543210 +0x01 intpri[7:0] intpri read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 00000000
113 8077b?avr?06/08 xmega a change the priority queue. this register is not reinitialized to its init ial value if round-robing scheduling is disabled, so if default static priority is needed the register must be written to zero. 11.8.3 ctrl - pmic control register ? bit 7 - rren: round-robin scheduling enable when the rren bit is set the round-robin schedu ling scheme is enabled fo r low level interrupts. when this bit is cleared, the priority is static according to interrupt vector address where the low- est address has the highest priority. ? bit 6 - ivsel: interrupt vector select when the ivsel bit is cleared (zero), the interrupt vectors are placed at the start of the applica- tion section in flash. when this bit is set (one), the interrupt vectors are moved to the beginning of the boot section of the flash. refer to the device data sheet for the absolute address. this bit is protected by the configuratio n change protection mechanism, refer to ?configuration change protection? on page 12 for details. ? bit 5:3 - res: reserved these bits are unus ed and reserved for future use. for compatibility with futu re devices, always write these bits to zero when this register is written. ? bit 2 - hilvlen: high level interrupt enable when this bit is set all high level interrupts are enabled. if this bit is cleared, high level interrupt requests will be ignored. ? bit 1 - medlvlen: medium level interrupt enable when this bit is set all medium level interrupts ar e enabled. if this bit is cleared, medium level interrupt requests will be ignored. ? bit 0 - lolvlen: low level interrupt enable when this bit is set all low level interrupts are enabled. if this bit is cleared, low level interrupt requests will be ignored. 11.9 register summary bit 765432 1 0 +0x02 rren ivsel - - - hilvlen medlvlen lolvlen ctrl read/write r/w r/w r r r r/w r/w r/w initial value 000000 0 0 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page +0x00 status nmiex - - - - hilvlex medlvlex lolvlex 112 +0x01 intpri intpri[7:0] 112 +0x02 ctrl rren ivsel - - - hilvlen medlvlen lolvlen 113
114 8077b?avr?06/08 xmega a 12. i/o ports 12.1 features ? selectable input and output configuration for each pin individually ? flexible pin configuration through dedicated pin configuration register ? synchronous and/or asynchronous input sensing with port interrupts and events ? asynchronous wake-up signalling ? highly configurable output driver and pull settings: ? totem-pole ? pull-up/-down ? wired-and ? wired-or ? bus keeper ? inverted i/o ? slew rate control ? flexible pin masking ? configuration of multiple pins in a single operation ? read-modify-write (rmw) support ? toggle/clear/set registers for out and dir registers ? clock output on port pin ? event channel 7 output on port pin ? mapping of port registers (virtual port s) into bit accessible i/o memory space 12.2 overview xmega has flexible general purpose i/o (gpio) ports. a port consists of up to 8 pins ranging from pin 0 to 7, where each pin can be confi gured as input or output with highly configurable driver and pull settings. the ports also implement several functions including interrupts, synchro- nous/asynchronous input sensing an d asynchronous wa ke-up signalling. all functions are individual per pin, but several pi ns may be configured in a single operation. all ports have true read-modify-write (rmw) functionality when used as general purpose i/o ports. the direction of one port pin can be changed without unintentionally changing the direction of any other pin. the same applies when changing drive value when configured as output, or enabling/disabling of pull-up or pull-down resistors when configured as input. figure 12-1 on page 115 shows the i/o pin functionality, and t he registers that is available for controlling a pin.
115 8077b?avr?06/08 xmega a figure 12-1. general i/o pin functionality. 12.3 using the i/o pin use of an i/o pin is controlled from the user software. each port has one data direction (dir), data output value (out) that is used for port pin control. the data input value (in) register is used for reading the port pins. in addition each pin has a pin configuration (pinnctrl) register for additional pin configuration. direction of the pin is decided by the dirn bit in the dir register. if dirn is written to one, pin n is configured as an output pin. if dirn is written to zero, pin n is configured as an input pin. when direction is set as output, the outn bit in out is used to set the value of the pin. if outn is written to one, pin n is driven high. if ou tn is written to zero , pin n is driven low. the in register is used for reading the pin value. the pin value can always be read regardless of the pin being configured as input or output, except if digital input is disabled. i/o pins are tri-stated when reset condition becomes active, even if no clocks are running. d q r d q r digital input disable d q r synchronizer d q r d q r wired or wired and slew rate limit enable outn dirn pinnctrl pull enable pull keep pull direction inn pn reset reset reset inverted i/o
116 8077b?avr?06/08 xmega a 12.4 i/o pin configuration the pin n configuration (pinnctrl) register is us ed for additional i/o pin configuration. a pin can be set in a totem-pole, wired -and, or wired-or configuration. it is also possible to enable inverted input and output for the pin. for totem-pole output there are four possible pull configurations: totem-pole (push-pull), pull- down, pull-up and bus-keeper. the bus-keeper is active in both directions. this is to avoid oscil- lation when disabling the output. the totem-pole configurations with pull-up and pull-down only have active resistors when the pin is set as input. this feature eliminates unnecessary power consumption. for wired-and and wired-or configuration, the optional pull-up and pull-down resistors are active in both input and output direction. since pull configuration is configured through the pin configuration register, all intermediate port states during switching of pin direction and pin values are avoided. the i/o pin configurations are summarized with simplified schematics from figure 12-2 on page 116 to figure 12-7 on page 118 . 12.4.1 totem-pole figure 12-2. i/o pin configuration - totem-pole (push-pull). 12.4.2 pull-down figure 12-3. i/o pin configuration - totem-pole with pull-down (on input). inn outn dirn pn inn outn dirn pn
117 8077b?avr?06/08 xmega a 12.4.3 pull-up figure 12-4. i/o pin configuration - totem-pole with pull-up (on input). 12.4.4 bus-keeper the bus-keeper?s week output produces the same logi cal level as the last output level. it acts as a pull-up if the last leve l was '1', and pull-down if the last level was '0'. figure 12-5. i/o pin configuration - totem-pole with bus-keeper. inn outn dirn pn inn outn dirn pn
118 8077b?avr?06/08 xmega a 12.4.5 wired-or figure 12-6. output configuration - wired-or with optional pull-down. 12.4.6 wired-and figure 12-7. output configuration - wired-and with optional pull-up. 12.5 reading the pin value independent of the pin data direction, the pin value can be read from the in register as shown in figure 12-1 on page 115 . if the digital input is disabled, the pin value cannot be read. the in register bit and the preceding flip-flop constitu te a synchronizer. the synchronizer is needed to avoid metastability if the physical pin changes value near the edge of the internal clock. the synchronizer introduces a delay on the internal signal line. figure 12-8 on page 119 shows a timing diagram of the synchronization when reading an externally applied pin value. the maxi- mum and minimum propagation delays are denoted t pd,max and t pd,min respectively. inn outn pn inn outn pn
119 8077b?avr?06/08 xmega a figure 12-8. synchronization when reading an externally applied pin value. 12.6 input sense configuration input sensing is used to detect an edge or level on the i/o pin input. the different sense configu- rations that are available for ea ch pin are detection of rising edge, falling edge or both edges, or detection of low level. high level can be detecte d by using inverted input. input sensing can be used to trigger interrupt requests (ireq) or events when there is a change on the pin. the i/o pins support synchronous and asynchronous input sensing. synchronous sensing requires presence of the peripheral clock, while asynchronous sensing does not require any clock. figure 12-9. input sensing. peripheral clk instructions sync flipflop in r17 xxx xxx lds r17, portx+in t pd, max t pd, min 0x00 0xff inverted i/o interrupt control ireq event pn d q r d q r synchronizer inn edge detect asynchronous sensing synchronous sensing edge detect
120 8077b?avr?06/08 xmega a 12.7 port interrupt each port has two interrupt vectors, and it is configurable which pins on the port that can be used to trigger each interrupt request. port interrupts must be enabled before they can be used. which sense configurations that can be used to generate interrupts is dependent on whether synchronous or asynchronous input sensing is used. for synchronous sensing, all sense configurations can be used to generate interrupts. for edge detection, the changed pin value must be sampled once by the peripheral clock for an interrupt request to be generated. for asynchronous sensing, only port pin 2 on each port has full asynchronous sense support. this means that for ed ge detection, pin 2 will de tect and latch any edge and it will a lways trigger an interrupt request. the other port pins have limited asynchronous sense support. this means that for edge detection the changed value must be held until the device wakes up and a clock is present. if the pin value returns to its initial value before the end of the device start-up time, the device will still wake up, but no in terrupt request will be generated. a low level can always be detected by all pins, regardless of a peripheral clock being present or not. if a pin is configured for lo w level sensing, the in terrupt will trigger as lo ng as the pin is held low. in active mode the low level must be kept until the completion of the currently executing instructions for an interrupt to be generated. in all sleep modes the low level must be kept until the end of the device start-up time for an interrupt to be generated. if the low level disappears before the end of the st art-up time, the device will still wa ke up, but no interrupt will be generated. table 12-1 , table 12-2 , and table 12-3 on page 121 summarizes when interrupts can be trig- gered for the various input sense configurations. table 12-1. synchronous sense support sense settings supported interrupt description rising edge yes always triggered falling edge yes always triggered both edges yes always triggered low level yes pin-level must be kept unchanged. table 12-2. full asynchronous sense support sense settings supported interrupt description rising edge yes always triggered falling edge yes always triggered both edges yes always triggered low level yes pin-level must be kept unchanged.
121 8077b?avr?06/08 xmega a 12.8 port event port pins can generate an event when there is a change on the pin. the sense configurations decide when each pin will generat e events. event generation requi res the presence of a periph- eral clock, hence asynchronous event generation is not possible. for edge sensing, the changed pin value must be sampled once by the peripheral clock for an event to be generated. for low level sensing, events gene ration will follow the pin value. a pin change from high to low (falling edge) will not generate an event, the pin change must be from low to high (rising edge) for events to be generated. in order to generate events on falling edge, the pin configuration must be set to inverted i/o. a low pin value will not ge nerate events, and a high pin value will cont inuously generate events. 12.9 alternate port functions most port pins have alternate pin functions in addition to being a general purpose i/o pin. when an alternate function is enabled this might overri de the normal port pin function or pin value. this happens when other peripherals that require pins are enabled or configured to use pins. if, and how a peripheral will override and use pins is described in the data sheet module for each peripheral. the port override signals and related logic (grey) is shown in figure 12-10 on page 122 . these signals are not accessible from software, but are internal signals between the overriding periph- eral and the port pin. table 12-3. limited asynchronous sense support sense settings supported interrupt description rising edge no - falling edge no - both edges yes pin value must be kept unchanged. low level yes pin-level must be kept unchanged.
122 8077b?avr?06/08 xmega a figure 12-10. port override signals and related logic 12.10 slew-rate control slew-rate control can be enabled for all i/o pins individually. enabling t he slew rate limiter will typically increase the rise/fall time by 50-150% depending on voltage, temperature and load. for information about the characteristics of the sl ew-rate limiter, please refer to the device data sheet. 12.11 clock and event output it is possible to output both the peripheral clock and the signaling event from event channel 0 to pin. output port pin is selected from softw are. event channel 7 from the event system can d q r d q r digital input enable (die) d q r synchronizer d q r d q r wired or wired and slew rate limit enable outn dirn pinnctrl pull enable pull keep pull direction inn pn reset reset reset inverted i/o d' d' d' enable d' enable q' q' enable q' q' enable die override value die override enable pull disable inverted i/o disable input synch disable
123 8077b?avr?06/08 xmega a also be output on a port pin. if an event occur on event channel 7, this will be visible on the port pin as long as the event last. normally th is is one peripheral clock cycle only. 12.12 multi-configuration mpcmask can be used to set a bi t mask for the pin configuration registers. when setting bit n in mpcmask, pinnctrl is added to the pin configuration mask. duri ng the next wr ite to any of the port's pin config uration registers, the same value will be written to all the port's pin configura- tion registers set by the mask. the mpcmask register is cleared automatically after the write operation to the pin configuration registers is finished. 12.13 virtual registers virtual port registers allows for port registers in the extended i/o memory space to be mapped virtually in the i/o memory space. when mapping a port, writing to the virtual port register will be the same as writing to the real port register. this enables use of i/o memory specific instructions for bit-manipulation, and the i/o memory specific instructions in and out on port register that normally resides in the extended i/o memory space. there are four virtual ports, so up to four ports can be mapped virtually at the same time. the mapped registers are in, out, dir and intflags. 12.14 register d escription ? ports 12.14.1 dir - data direction register ? bit 7:0 - dir[7:0]: data direction this register sets the data direction for the individua l pins in the port. if dirn is written to one, pin n is configured as an output pin. if dirn is written to zero, pin n is configured as an input pin. 12.14.2 dirset - data direction set register bit 76543210 +0x00 dir[7:0] dir read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 +0x01 dirset[7:0] dirset read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000
124 8077b?avr?06/08 xmega a ? bit 7:0 - dirset[7:0]: port data direction set this register can be used instead of a read-modify-write to set individual pins as output. writing a one to a bit will set the corresponding bit in th e dir register. reading this register will return the value of the dir register. 12.14.3 dirclr - data di rection clear register ? bit 7:0 - dirclr[7:0]: po rt data direction clear this register can be used instead of a read-modify-write to set individual pins as input. writing a one to a bit will clear the corresponding bit in the dir register. reading this register will return the value of the dir register. 12.14.4 dirtgl - data direction toggle register ? bit 7:0 - dirtgl[7:0]: port data direction toggle this register can be used instead of a read-modify-write to toggle the direction on individual pins. writing a one to a bit will toggle the corres ponding bit in the dir register. reading this reg- ister will return the valu e of the dir register. 12.14.5 out - data output value ? bit 7:0 - out[7:0]: port data output value this register sets the data output value for the i ndividual pins in the port. if outn is written to one, pin n is driven high. if outn is written to zero, pin n is driven low. for this setting to have any effect the pin direction must be set as output. bit 76543210 +0x02 dirclr[7:0] dirclr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 +0x03 dirtgl[7:0] dirtgl read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 +0x04 out[7:0] out read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000
125 8077b?avr?06/08 xmega a 12.14.6 outset - data output value set register ? bit 7:0 - outset[7:0]: data output value set this register can be used instead of a read-modi fy-write to set the output value on individual pins to one. writing a one to a bit will set the corresponding bit in the out register. reading this register will return the value in the out register. 12.14.7 outclr - data output value clear register ? bit 7:0 - outclr[7:0]: data output value clear this register can be used instead of a read-modi fy-write to set the output value on individual pins to zero. writing a one to a bit will clear the corresponding bit in the out register. reading this register will re turn the value in the out register. 12.14.8 outtgl - data output value toggle register ? bit 7:0 - outtgl[7:0]: port data output value toggle this register can be used instead of a read-modify-write to toggle the output value on individual pins. writing a one to a bit will toggle the corresp onding bit in the out regi ster. reading this reg- ister will return the valu e in the out register. 12.14.9 in - data input value register bit 76543210 +0x05 outset[7:0] outset read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 +0x06 outclr[7:0] outclr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 +0x07 outtgl[7:0] outtgl read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 +0x08 in[7:0] in read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000
126 8077b?avr?06/08 xmega a ? bit 7:0 - in[7:0]: data input value this register shows the value present on the pins if the digital input driver is enabled. inn shows the value of pin n on the port. 12.14.10 intctrl - interrupt control register ? bit 7:4 - res: reserved these bits are unus ed and reserved for future use. for compatibility with futu re devices, always write these bits to zero when this register is written. ? bit 3:2/1:0 - intnlvl[1:0]: interrupt n level these bits enable interrupt request for port interrupt n and select the interrupt level as described in ?interrupts and programmable multi-level interrupt controller? on page 108 . 12.14.11 int0mask - interrupt 0 mask register ? bit 7:0 - int0msk[7:0]: interrupt 0 mask register these bits are used to mask which pins can be used as sour ces for port interrupt 0. if int0maskn is written to one, pin n is used as source for port interr upt 0.the input sense config- uration for each pin is decided by the pinnctrl-registers. 12.14.12 int1mask - interrupt 1 mask register ? bit 7:0 - int1mask[7:0]: interrupt 1 mask register these bits are used to mask which pins can be used as sour ces for port interrupt 1. if int1maskn is written to one, pin n is used as source for port interr upt 1.the input sense config- uration for each pin is decided by the pinnctrl-registers. bit 76543210 +0x09 - - - - int1lvl[1:0] int0lvl[1:0] intctrl read/write r r r r r/w r/w r/w r/w initial value00000000 bit 76543210 +0x0a int0msk[7:0] int0mask read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 +0x0b int1msk[7:0] int1mask read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000
127 8077b?avr?06/08 xmega a 12.14.13 intflags - interrupt flag register ? bit 7:2 - res: reserved these bits are reserved and will always be read as zero. for compatibility with future devices, always write these bits to zero when this register is written. ? bit 1:0 - intnif: interrupt n flag the intnif flag is set when a pin change according to the pin's input sense configuration occurs, and the pin is set as source for port interrupt n. writing a one to this flag's bit location will clear the flag. for enabling and executing the interrupt refer to the interrupt level description. 12.14.14 pinnctrl - pin n configuration register ? bit 7 - srlen: slew rate limit enable setting this bit will enable slew-rate limiting on pin n. ? bit 6 - inven: inverted i/o enable setting this bit will enable invertin g output and input data on pin n. ? bit 5:3 - opc: output and pull configuration these bits sets the output/pull configuration on pin n according to table 12-4 . bit 76543210 +0x0c ------int1ifint0ifin tflags read/writerrrrrrr/wr/w initial value00000000 bit 76543210 srlen inven opc[2:0] isc[2:0] pinnctrl read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 table 12-4. output/pull configuration opc[2:0] group configuration description output configuration pull configuration 000 totem totempole (n/a) 001 buskeeper totempole bus keeper 010 pulldown totempole pull-down (on input) 011 pullup totempole pull-up (on input) 100 wiredor wired_or (n/a) 101 wiredand wired_and (n/a) 110 wiredorpull wired_or pull-down 111 wiredandpull wired_and pull-up
128 8077b?avr?06/08 xmega a ? bit 2:0 - isc[2:0]: input/sense configuration these bits sets the input and sense configuration on pin n according to table 12-5 . the sense configuration decides how the pin can trigger port interrupts and events. when the input buffer is not disabled, the schmitt triggered input is sampled (synchronized) and can be read in the in register. note: 1. a low pin value will not generate events, and a high pin value will continuously generate events. 2. only port a - f supports the input buffer disable option. 12.15 register descr iption ? multipor t configuration 12.15.1 mpcmask - multi-pin configuration mask register ? bit 7:0 - mpcmask[7:0]: multi-pin configuration mask the mpcmask register enables severa l pins in a port to be configur ed at the same time. writing a one to bit n allows that pin to be part of the multi-pin configuration. when a pin configuration is written to one of the pinnctrl registers of the port, that value is written to all the pinnctrl registers of the pins matching t he bit pattern in the mp cmask register for that port. it is not nec- essary to write to one of the registers that is set by the mpcmask register. the mpcmask register is automatically cleared afte r any pinnctrl regi sters is written. 12.15.2 vpctrla - virtual port-map control register a table 12-5. input/sense configuration isc[2:0] group configuration description 000 bothedges sense both edges 001 rising sense rising edge 010 falling sense falling edge 011 level sense low level (1) 100 reserved 101 reserved 110 reserved 111 intput_disable input buffer disabled (2) bit 76543210 +0x00 mpcmask[7:0] mpcmask read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 +0x02 vp1map[3:0] vp0map[3:0] vpctrla read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0
129 8077b?avr?06/08 xmega a ? bit 7:4 - vp1map: vi rtual port 1 mapping these bits decide which ports should be mapped to virtual port 1. the registers dir, out, in and intflags will be mapped. acce ssing the virtual port register s is equal to accessing the actual port registers. see table 12-6 for configuration. ? bit 3:0 - vp0map: vi rtual port 0 mapping these bits decide which ports should be mapped to virtual port 0. the registers dir, out, in and intflags will be mapped. acce ssing the virtual port register s is equal to accessing the actual port registers. see table 12-6 for configuration. 12.15.3 vpctrlb - virtual port-map control register b ? bit 7:4 - vp3map: vi rtual port 3 mapping these bits decide which ports should be mapped to virtual port 3. the registers dir, out, in and intflags will be mapped. acce ssing the virtual port register s is equal to accessing the actual port registers. see table 12-6 for configuration. ? bit 3:0 - vp2map: vi rtual port 2 mapping these bits decide which ports should be mapped to virtual port 2. the registers dir, out, in and intflags will be mapped. acce ssing the virtual port register s is equal to accessing the actual port registers. see table 12-6 for configuration. bit 76543210 +0x03 vp3map[3:0] vp2map[3:0] vpctrlb read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 table 12-6. virtual port mapping. vpnmap[3:0] group configuration description 0000 porta porta mapped to virtual port n 0001 portb portb mapped to virtual port n 0010 portc portc mapped to virtual port n 0011 portd portd mapped to virtual port n 0100 porte porte mapped to virtual port n 0101 portf portf mapped to virtual port n 0110 portg portg mapped to virtual port n 0111 porth porth mapped to virtual port n 1000 portj portj mapped to virtual port n 1001 portk portk mapped to virtual port n 1010 portl portl mapped to virtual port n 1011 portm portm mapped to virtual port n 1100 portn portn mapped to virtual port n
130 8077b?avr?06/08 xmega a 12.15.4 clkevout - clock and event out register ? bit 7:6 - res: reserved these bits are reserved and will always be read as one. for compatibility with future devices, always write these bits to zero when this register is written. ? bit 5:4 - evout[1:0] - event output port these bits decide which port the event channel 0 from the event system should be output to. pin 7 on the selected port is always used, and the clkout bits must be set different from evout. the pin must be configured as an output pin for the signaling event to be available on the pin. table 12-7 on page 130 shows the possible configurations. ? bits 3:2 - res: reserved these bits are reserved and will always be read as one. for compatibility with future devices, always write these bits to zero when this register is written. ? bit 1:0 - clkout[1:0] - clock output port these bits decide which port the peripheral cloc k should be output to. pin 7 on the selected port is always used. the clock output setting, will ov erride the event output setting, thus if both are enabled on the same port pin, the peripheral clock will be vi sible. the pin must be configured as an output pin for the clock to be available on the pin. table 12-8 on page 131 shows the possible configurations. 1101 portp portp mapped to virtual port n 1110 portq portq mapped to virtual port n 1111 portr portr mapped to virtual port n table 12-6. virtual port mapping. (continued) vpnmap[3:0] group configuration description bit 76543210 +0x04 - - evout[1:0] - - clkout[1:0] clkevout read/write r r r/w r/w r r r/w r/w initial value 0 0 0 0 0 0 0 0 table 12-7. event channel 7 output configurations evout[1:0] group configuration description 00 off event out disabled 01 pc7 event channel 7 output on port c pin 7 10 pd7 event channel 7 output on port d pin 7 11 pe7 event channel 7 output on port e pin 7
131 8077b?avr?06/08 xmega a 12.16 register descrip tion ? virtual port 12.16.1 dir - data direction ? bit 7:0 - dir[7:0]: data direction register this register sets the data direction for the individual pins in the port mapped by "vpctrla - virtual port-map control register a" or "vpctr lb - virtual port-map control register b". when a port is mapped as virtual, accessing this regist er is identical to accessing the actual dir regis- ter for the port. 12.16.2 out - data output value ? bit 7:0 - out[7:0]: data output value this register sets the data output value for th e individual pins in th e port mapped by "vpctrla - virtual port-map control register a" or "vpc trlb - virtual port-map control register b". when a port is mapped as virtual, accessing this register is identical to accessing the actual out register for the port. 12.16.3 in - data input value table 12-8. clock output configurations clkout[1:0] group configuration description 00 off clock out disabled 01 pc7 clock output on port c pin 7 10 pd7 clock output on port d pin 7 11 pe7 clock output on port e pin 7 bit 76543210 +0x00 dir[7:0] dir read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 +0x01 out[7:0] out read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 +0x02 in[7:0] in read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000
132 8077b?avr?06/08 xmega a ? bit 7:0 - in[7:0]: data input value this register shows the value present on the pins if the digital input buffer is enabled. the config- uration of "vpctrla - virtual port-map control register a" or "vpctrlb - virtual port-map control register b" decides the value in the regi ster. when a port is mapped as virtual, access- ing this register is identical to accessing the actual in register for the port. 12.16.4 intflags - interrupt flag register ? bit 7:2 - res: reserved these bits are reserved and will always be read as zero. for compatibility with future devices, always write these bits to zero when this register is written. ? bit 1:0 - intnif: interrupt n flag the intnif flag is set when a pin change according to the pin's input sense configuration occurs, and the pin is set as source for port interrupt n. writing a one to this flag's bit location will clear the flag. for enabling and executing the inte rrupt refer to the interrupt level description. the configuration of "vpctrla - virtual port-ma p control register a" or "vpctrlb - virtual port-map control register b" decides which the flags mapped. when a port is mapped as vir- tual, accessing this register is identical to acce ssing the actual intflags register for the port. bit 76543210 +0x03 - - - - - - int1if int0if intflags read/writerrrrrrr/wr/w initial value00000000
133 8077b?avr?06/08 xmega a 12.17 register summary ? ports 12.18 register summary ? port configuration 12.19 register summary ? virtual ports address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page +0x00 dir dir[7:0] 123 +0x01 dirset dirset[7:0] 123 +0x02 dirclr dirclr[7:0] 124 +0x03 dirtgl dirtgl[7:0] 124 +0x04 out out[7:0] 124 +0x05 outset outset[7:0] 125 +0x06 outclr outclr[7:0] 125 +0x07 outtgl outtgl[7:0] 125 +0x08 in in[7:0] 125 +0x09 intlvl - - - - int1lvl[1:0] int0lvl[1:0] 126 +0x0a int0mask int0msk[7:0] 126 +0x0b int1mask int1msk[7:0] 126 +0x0c intflags - - - - - - int1if int0if 127 +0x0d reserved - - - - - - - - +0x0e reserved - - - - - - - - +0x0f reserved - - - - - - - - +0x10 pin0ctrl srlen inven opc[2:0] isc[2:0] 127 +0x11 pin1ctrl srlen inven opc[2:0] isc[2:0] 127 +0x12 pin2ctrl srlen inven opc[2:0] isc[2:0] 127 +0x13 pin3ctrl srlen inven opc[2:0] isc[2:0] 127 +0x14 pin4ctrl srlen inven opc[2:0] isc[2:0] 127 +0x15 pin5ctrl srlen inven opc[2:0] isc[2:0] 127 +0x16 pin6ctrl srlen inven opc[2:0] isc[2:0] 127 +0x17 pin7ctrl srlen inven opc[2:0] isc[2:0] 127 +0x18 reserved - - - - - - - - +0x19 reserved - - - - - - - - +0x1a reserved - - - - - - - - +0x1b reserved - - - - - - - - +0x1c reserved - - - - - - - - +0x1d reserved - - - - - - - - +0x1e reserved - - - - - - - - +0x1f reserved - - - - - - - - address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page +0x00 mpcmask mpcmask[7:0] 128 +0x01 reserved - - - - - - - - +0x02 vpctrla vp1map[3:0] vp2map[3:0] 128 +0x03 vpctrlb vp3map[3:0] vp4map[3:0] 129 +0x04 clkevout evout[1:0] clkout[1:0] 130 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page +0x00 dir dir[7:0] 131 +0x01 out out[7:0] 131 +0x02 in in[7:0] 131 +0x03 intflags - - - - - - int1if int0if 132
134 8077b?avr?06/08 xmega a 13. tc - 16-bit timer/counter 13.1 features ? 16-bit timer/counter ? double buffered timer period setting ? up to 4 combined compare or capture (cc) ch annels (a, b, c, and d) ? all compare or capture channels are double buffered ? waveform generation: ? single slope pulse width modulation ? dual slope pulse width modulation ? frequency generation ? input capture: ? input capture with noise cancelling ? frequency capture ? pulse width capture ? 32-bit input capture direction control ? timer overflow and timer error interrupts / events ? one compare match or capture interrupt / event per cc channel ? supports dma operation ? hi-res- hi-resolu tion extension ? increases pwm/frq resolution by 2-bits (4x) ? awex - advanced waveform extension ? 4 dead-time insertion (dt) units with separate high- and low-side settings ? event controlled fault protection ? single channel multiple output operation ? pattern generation 13.2 overview xmega has a set of high-end and very flexible 16-bit timer/coun ters (tc). thei r basic capabili- ties include accurate program execution timing, frequency and waveform generation, event management, and time measurement of digital signals. the hi-resolution extension (hi-res) and advanced waveform extension (awex) can be used together with a timer/counter to ease implementation of more advanced and specialized frequency and waveform generation features. a block diagram of the 16-bit timer/counter with extensions and closely related peripheral mod- ules (in grey) is shown in figure 13-1 on page 135 .
135 8077b?avr?06/08 xmega a figure 13-1. 16-bit timer/counter and closely related peripheral the time/counter consists of a base counter and a set of compare or capture (cc) channels. the base counter can be used to count clock cycles or events. it has direction control and period setting that can be used for timing. th e cc channels can be used together with the base counter to do compare match control, waveform generation (frq or pwm) or various input cap- ture operations. compare and capture cannot be done at the same time, i.e. a single timer/counter cannot simultaneously perform both waveform generation and capture operation. when used for com- pare operations, the cc channels is referred to as compare channels. when used for capture operations, the cc channels are referred to as capture channels. the timer/counter comes in two versions: timer/counter 0 that has four cc channels, and timer/counter 1 that has two cc channels. hence, all registers and register bits that are related to cc channel 3 and cc channel 4 w ill only exist in timer/counter 0. all timer/counter units are connected to the common peripheral clock prescaler, the event sys- tem, and their corresponding general purpose i/o port. some of the timer/counters will have extensions . the function of the timer/counter extensions can only be performed by these timers. the advanced waveform extension (awex) can be used for dead time insertion, pattern generation and fault protection. the awex extension is only available for timer/counter 0. waveform outputs from a timer/counter can optionally be passed through to a hi-resolution (hi-res) extension before forwarded to the port. this extension, running at up to four times the peripheral clock fr equency, to enhanc e the resolution by four times. all timer/counters will have the hi-res extention. awex compare/capture channel d compare/capture channel c compare/capture channel b compare/capture channel a waveform generation buffer comparator hi-res fault protection capture control base counter counter control logic timer period prescaler dti dead-time insertion pattern generation clk per4 ports event system clk per timer/counter
136 8077b?avr?06/08 xmega a 13.2.1 definitions the following definitions are used extensively throughout the timer/counter documentation: in general the term timer is used when the timer/counter clock control is handled by an internal source and the term counter is used if th e clock is given externally (from an event). 13.3 block diagram figure 13-2 on page 137 shows a detailed block diagram of the timer/counter without the extensions. table 13-1. timer/counter definitions name description bottom the counter reaches the bottom when it becomes zero. max the counter reaches maximum when it becomes all ones. top the counter reaches the top when it becomes equal to the highest value in the count sequence. the top value can be equal to the period (per) or the compare channel a (cca) register setting. this is selected by the waveform generator mode. update the timer/counter signalizes an update when it reaches bottom or top dependent of the waveform generator mode.
137 8077b?avr?06/08 xmega a figure 13-2. timer/counter block diagram the counter register (cnt), the period registers w/buffer (per and perbuf), and the com- pare and capture registers w/buffers (ccx and ccxbuf) are 16-bit registers. during normal operation the counter value is c ontinuously compared to zero and the period (per) value to determine whether the counter has reached top or bottom. the counter value is also compared to the ccx registers. these comparators can be used to generate interrupt requests or request dma transactions. they also generate events for the event system. the waveform generator modes use the comparators to set the waveform period or pulse width. a prescaled peripheral clock and events from t he event system can be used for controlling the counter. the event system is also used as source to the input capture. combined with the quadrature decoding functionality in the event system qdec, the timer/counter can be used for high speed quadrature decoding. base counter bus bridge compare/capture (x = {a,b,c,d}) counter = ccx ccxbuf waveform generation v = perbuf per cnt v = 0 "count" "clear" "direction" "load" control logic evsel event select cksel clock select ovf/unf (int/dma req.) errif (int req.) top "match" ccxif (int/dma req.) control logic "capture" i/o data bus (16-bit) i/o data bus (8-bit) "ev" update bottom temp ctrl a b d ocx out c e intctrl a b g intflags
138 8077b?avr?06/08 xmega a 13.4 clock and event sources the timer/counter can be clocked from the peripheral clock (clk per ) and from the event sys- tem, and figure 13-3 shows the clock and event selection logic. figure 13-3. clock and event selection the peripheral clock is fed into the common prescaler (common for all timer/counters in a device). a selection of the prescaler outputs is di rectly available for the timer/counter. in addi- tion the whole range from 1 to 2 15 times prescaling is available through the event system. each timer/counter has separate clock selection (clksel), to select on e of the prescaler out- puts directly or an event channel as the counter (cnt) input. this is referred to as normal operation for the counter, for details refer to ?normal operation? on page 140 . by using the event system, any event source such as an external clock signal on any i/o pin can be used as clock input. in addition the timer/counter can be controlled via the event system. the event selection (evsel) and event action (evact) settings can be used to trigger an even t action from one or more events. this is referred to as event action controlled operation for the counter, for details refer to ?event action controlled operation? on page 140 . when event action controlled opera- tion is used, the clock selection must be set to us an event channel as the counter input. by default no clock input is selected and the timer/counter is not running (off state). 13.5 double buffering the period register and the cc registers are all double buffered. each buffer registers have an associated buffer valid (bv) flag, which indicate that the buffer contains a valid, i.e. a new value that is to be copied into the belonging period or compare register. for the period register and for the cc channels when used for compare operation, the buffer valid flag is set when data is writ- ten to the buffer register and cleared on update condition. this is shown for a compare register in figure 13-4 on page 139 . clk per / 2 {0,...,15} clksel cnt evact clk / {1,2,4,8,64,256,1024} common prescaler clk per event channels (encoding) event system evsel events control logic
139 8077b?avr?06/08 xmega a figure 13-4. period and compare double buffering when the cc channels is used for capture oper ation a similar double buffering mechanism is used, but the buffer valid flag is se t on the capture event as shown in figure 13-5 . for capture the buffer and the corresponding ccx register acts like a fifo. when the cc register is empty or read, any contents in the buffer is passed to the cc register. the buffer valid flag is passed to the ccx interrupt flag (if) which is them set and the optional interrupt is generated. figure 13-5. capture double buffering both the ccx and ccxbuf registers are available in the i/o register address map. this allows initialization and bypassing of the buffer register, and the double buffering feature. 13.6 counter operation dependent of the mode of operation, the counter is cleared, reloaded, incremented, or decre- mented at each timer/counter clock input. bv ccxbuf ccx update en i/o bus (16-bit) en "write enable" "data" = cnt "match" bv i/o bus (16-bit) "capture" if cnt ccxbuf ccx en en "int/dma request"
140 8077b?avr?06/08 xmega a 13.6.1 normal operation in normal operation the counter will count in the direction set by the direction (dir) bit for each clock until it reaches top or bottom. w hen top is reached when up-counting, the counter will be set to zero when the next clock is gi ven. when down-counting the counter is reloaded with period register value when bottom is reached. figure 13-6. normal mode of operation as shown in figure 13-6 changing the counter value while the counter is running is possible. the write access has higher priority than count, clear, or reload and will be immediate. the direction of the counter can also be changed during normal operation. normal operation must be used when using the counter as timer base for the capture channels. 13.6.2 event action controlled operation the event selection and event action settings c an be used to control the counter from the event system. for the counter the event actions can be selected to: ? event system controlled up/down counting. ? event system controlled quadrature decode counting. 13.6.3 32-bit operation two timer/counters can be used together to enabl e 32-bit counter operation. by using two timer/counters the overflow event from one ti mer/counter (least significant timer) can be routed via the event system and used as clock input for another timer/counter (most significant timer). 13.6.4 changing the period the counter period is changed by writing a new top value to the period register. if double buffering is not used, any period update is immediate as shown in figure 13-7 on page 141 . cnt bot max "update" top cnt written dir
141 8077b?avr?06/08 xmega a figure 13-7. changing the period without buffering when double buffering is used, the buffer can be written at any time, but the period register is always updated on the ?update? condition as shown in figure 13-8 . this prevents wraparound and generation of odd waveforms. figure 13-8. changing period using buffering 13.7 capture channel the cc channels can be used as capture channel to capture external events and give them a time-stamp indicating time of occurrence. to use capture the counter must be set in normal operation. events are used to trigger the capture, i.e any events from the event system including pin change from any pin can trigger a capture operation. the event action setting in the timer/counter will determine the ty pe of capture that is done. the cc channel to use must be enabled individually before capture can be done. when the cap- ture condition occu r, the timer/counter will time-stamp the event by copying the current value in the count register into the enabled cc channel register. three different types of capture are available. cnt max new top written to per that is higher than current cnt counter wraparound new top written to per that is lower than current cnt "update" "write" bot cnt max new period written to perbuf that is higher than current cnt new period written to perbuf that is lower than current cnt "update" "write" new per is updated with perbuf value. bot
142 8077b?avr?06/08 xmega a 13.7.1 input capture selecting the input capture event action, makes the enabled capture channel perform an input capture on any event. the interrupt flags will be set and indicate that there is a valid capture result in the corresponding cc register. equally t he buffer valid flags indicates valid data in the buffer registers. refer to ?double buffering? on page 138 for more details on capture double buffering. the counter will continuously co unt for bottom to top, then restart on bottom as shown in figure 13-9 . the figure also shows four capture events for one capture channel. figure 13-9. input capture timing 13.7.2 frequency capture selecting the frequency capture event action, makes the enabled capture channel perform a input capture and restart on any event. this enables timer/counter to use capture to measure the period or frequency of a signal directly. the capture result will be the time, t, from the previ- ous timer/counter restart and until the event occurred. this can be used to calculate the frequency, f, of the signal: figure 13-10 on page 143 shows an example where the period is measured twice for an exter- nal signal. given that the event source is a i/o pi n, the sense configuration for the pin must be set up to generate an event on rising edge only. for details on sense configuration on i/o pins, refer to ?input sense configuration? on page 119 . events cnt top bot capture 0 capture 1 capture 2 capture 3 f 1 t -- - =
143 8077b?avr?06/08 xmega a figure 13-10. frequency capture of an external signal since all capture channels uses the same c ounter (cnt), only one capture channels must be enabled at the time. if two capture channels are us ed with different source, the counter will be restarted on positive edge events from both input sources, and the result from the input capture will have no meaning. 13.7.3 pulse-width capture selecting the pulse-width measure event action makes the enabled compare channel perform the input capture ac tion on falling edge events and the rest art action on rising edge events. the counter will then start at zero at every star t of a pulse and the input capture will be performed at the end of the pulse. the event source must be an i/o pin and the sense configuration for the pin must be set up to generate an event on both edges. figure 13-11 on page 143 shows and exam- ple where the pulse width is measured twice for an external signal. figure 13-11. pulse-width capture of external signal. period (t) external signal events cnt max bot "capture" pulsewitdh (t p ) external signal events cnt max bot "capture"
144 8077b?avr?06/08 xmega a 13.7.4 32-bit input capture two timer/counters can be used together to enable true 32-bit input capture. in a typical 32-bit input capture setup the overflow event of the least significant timer is connected via the event system and used as clock input for the most significant timer. since all events are pipe lined, the most significant timer w ill be updated one peripheral clock period after an overflow occurs for the least significant timer. to compensate for this delay the capture event for the most significant timer must be equally delayed by setting the event delay bit for this timer. 13.7.5 capture overflow the timer/counter can detect buffer overflow on any of the input capture channels. in the case where both the buffer valid flag and capture interrupt flag are set, and a new capture event is detected there is nowhere to store the new time-s tamp. if a buffer overflow is detected the new value is rejected, the error interrupt flag is set and the optional interrupt is generated. 13.8 compare channel each compare channel continuously compares the counter value (cnt) with the ccx register. if cnt equals ccx the comparator signals a match. the match will set the cc channel's interrupt flag at the next timer clock cycle, and the event and optional interrupt is generated. the compare buffer register provides double buffer capability equivalent to the period buffer. the double buffering synchronizes the update of the ccx register with the buffer value to either the top or bottom of the counting sequence according to the update condition signal from the timer/counter control logic. the synchronization prevents the occurrence of odd-length, non-symmetrical pwm/frq pulses, thereby making the output glitch-free. 13.8.1 waveform generation the compare channels can be used for waveform generation on the corresponding port pins. to make the waveform visible on the connected port pin, the following requirements must be fulfilled: 1. a waveform generation mode must be selected. 2. event actions must be disabled. 3. the cc channels to be used must be enabl ed. this will override the corresponding port pin output register. 4. the direction for the associated port pin must be set to output. inverted waveform output can be achieved by setting the invert output bit for the port pin. 13.8.2 frequency (frq) waveform generation for frequency generation the period time (t) is controlled by the cca register instead of per, which in this case is not in use. the waveform generation (wg) output is toggled on each com- pare match between the cnt and cca registers as shown in figure 13-12 on page 145 .
145 8077b?avr?06/08 xmega a figure 13-12. frequency waveform generation the waveform generated will have a maximum frequency of half of the peripher al clock fre- quency (f per ) when cca is set to zero (0x0000). this also applies when using the hi-res extension since this only increase the resolution and not the frequency. the waveform fre- quency (f frq )is defined by the following equation: where n represents the prescaler divider used (1, 2, 4, 8, 64, 256, 1024, or event channel n). 13.8.3 single slope pwm generation for single slope pwm generation, the period (t) is controlled by the per, while ccx registers control the duty cycle of the wg output. figure 13-13 shows how the counte r counts from bot- tom to top then restarts from bottom. the waveform generator (wg) output is set on the compare match between the cnt and ccx registers, and cleared at top. figure 13-13. single slope pulse width modulation the per register defines the pwm resolution. the minimum resolution is 2-bit (per=0x0003), and maximum resolution is 16-bit (per=max). cnt max "update" top cnt written direction change period (t) bot wg output f frq f per 2 n cca+1 () ------------------------------- - = cnt max top period (t) "match" bot wg output ccx=bot ccx ccx=top "update"
146 8077b?avr?06/08 xmega a the following equation can be used for calculat e the exact resolution for single-slope pwm (r pwm_ss ): the single slow pwm frequency (f pwm_ss ) depends on the period setting (per) and the periph- eral clock frequency (f per ), and can be calculated by the following equation: where n represents the prescaler divider used (1, 2, 4, 8, 64, 256, 1024, or event channel n). 13.8.4 dual slope pwm for dual slope pwm generation, the period (t) is controlled by the per, while ccx registers control the duty cycle of the wg output. figure 13-14 shows how for dual slope pwm the counter counts repeatedly from bottom to top, and then from top to bottom. the wg output is. the waveform generator output is set on bottom, cleared on compare match when upcounting and set on compare match when down counting. figure 13-14. dual-slope pulse width modulation using dual-slope pwm result in a lower maximum operation frequency compared to the single- slope pwm operation. the period register (per) defines the pwm re solution. the minimum resolution is 2-bit (per=0x0003), and maximum resolution is 16-bit (per=max). the following equation can be used for calculate the exact resolution for dual-slope pwm (r pwm_ds ): r pwm_ss per 1 + () log 2 () log ----------------------------------- = f pwm_ss f per n per 1 + () ------------------------------ - = cnt max top period (t) bot wg output ccx=bot ccx ccx=top "match" "update" r pwm_ds per 1 + () log 2 () log ----------------------------------- =
147 8077b?avr?06/08 xmega a the pwm frequency depends on the period setting (per) and the peripheral clock frequency (f per ), and can be calculated by the following equation: n represents the prescaler divider used (1, 2, 4, 8, 64, 256, 1024, or event channel n). 13.8.5 port override for waveform generation to make the waveform generation available on the port pins the corresponding port pin direction must be set as output. the timer/counter will over ride the port pin values when the cc channel is enabled (ccenx) and a waveform generation mode is selected. figure 13-15 on page 147 shows the port override for timer/counter 0 and 1. for timer/counter 1, cc channel a to d will override port pin 0 to 3 output value (out xn) on the corresponding port pin (pxn). for timer/counter 1, cc channel a and b will overri de port pin 4 and 5. enabling inverted i/o on the port pin (invenxn) inverts the corresponding wg output. figure 13-15. port override for timer/counter 0 and 1 f pwm_ds f per 2 n per ------------------- - = outx0 ccena invenx0 outx1 ccenb invenx1 px0 px1 oc0a oc0b outx2 ccenc invenx2 outx3 ccend invenx3 px2 px3 oc0c oc0d outx4 ccena invenx4 outx5 ccenb invenx5 px4 px5 oc1a oc1b wg 0a wg 0b wg 0c wg 0d wg 1a wg 1b
148 8077b?avr?06/08 xmega a 13.9 interrupts and events the t/c can generate both interrupts and events. the counter can generate an interrupt on overflow/underflow, and each cc channel has a separate interrupt that is used for compare or capture. in addition the t/c can generate an error interrupt if any of the cc channels is used for capture and a buffer overflow condition occurs on a capture channel. event will be generated for all conditi ons that can generate interrupts. for de tails on event gen- eration and available events refer to ?event system? on page 56 . 13.10 dma support. the interrupt flags can be used to trigger dma transactions. table 13-2 on page 148 lists the transfer triggers available from t he t/c, and the dma ac tion that will clear t he transfer trigger. for more details on using dma refer to ?dmac - direct memory access controller? on page 41 . 13.11 timer/counter commands a set of commands can be given to the timer/co unter by software to immediately change the state of the module. these commands give direct control of the update, restart, and reset signals. an update command has the same effect as when an update condition occurs. the update com- mand is ignored if the lock update bit is set. the software can force a restart of the current waveform period by issuing a restart command. in this case the counter, direction, and all compare outputs are set to zero. a reset command will set all timer/ counter registers to their init ial values. a reset can only be given when the timer/counter is not running (off). table 13-2. dma request sources request acknowledge comment ov/unfif dma controller writes to cnt dma controller writes to per dma controller writes to perbuf errif n/a ccxif dma controller access of ccx dma controller access of ccxbuf input capture operation output compare operation
149 8077b?avr?06/08 xmega a 13.12 register description 13.12.1 ctrla - control register a ? bit 7:4 - res: reserved bits these bits are unus ed and reserved for future use. for compatibility with futu re devices, always write these bits to zero when this register is written. ? bit 3:0 - clksel[3:0]: clock select these bits select clock source for the timer/counter according to table 13-3 . clksel=0001 must be set to ensure a correct output from the waveform generator when the hi-res extension is enabled. 13.12.2 ctrlb - control register b ? bit 7:4 ? ccxen: compare or capture enable setting these bits in frq or pwm waveform gener ation mode of operatio n will override of the port output register for the corresponding ocn output pin. when input capture operation is selected the ccxen bits enables the capture operation for the corresponding cc channel. bit 76543210 +0x00 ---- clksel[3:0] ctrla read/write r r r r r/w r/w r/w r/w initial value00000000 table 13-3. clock select clksel[3:0] group configuration description 0000 off none (i.e, timer/ counter in ?off? state) 0001 div1 prescaler: clk 0010 div2 prescaler: clk/2 0011 div4 prescaler: clk/4 0100 div8 prescaler: clk/8 0101 div64 prescaler: clk/64 0110 div256 prescaler: clk/256 0111 div1024 prescaler: clk/1024 1xxx evchn event channel n, n= [0,...,7] bit 76543210 +0x01 ccden cccen ccben ccaen - wgmode[2:0] ctrlb read/write r/w r/w r/w r/w r r/w r/w r/w initial value 0 0 0 0 0 0 0 0
150 8077b?avr?06/08 xmega a ? bit 3 ? res: reserved this bit is unused and reserved fo r future use. for comp atibility with future devices, always write this bit to zero when this register is written. ? bit 2:0 ? wgmode[2:0]: waveform generation mode these bits select the waveform generation mode, and control the counting sequence of the counter, the top value, the update condition, the interrupt/event condition, and type of wave- form that is generated, according to table 13-4 on page 150 . no waveform generation is performed in normal mode of operation. for all other modes the result from the waveform generator will only be directed to the port pins if the corresponding ccxen bit has been set to enable this. the port pin direction must be set as output. 13.12.3 ctrlc - control register c ? bit 7:4 ? res: reserved these bits are unus ed and reserved for future use. for compatibility with futu re devices, always write these bits to zero when this register is written. ? bit 3:0 ? cmpx: compare output value n these bits allow direct access to the waveform generator's output compare value when the timer/counter is set in ?off? state. this is used to set or clear the wg output value when the timer/counter is not running. table 13-4. timer waveform generation mode wgmode[2:0] group configuration mode of operation top update ovfif/event 000 normal normal per top top 001 frq frq cca top top 010 reserved - - - 011 ss single slope pwm per bottom bottom 100 reserved - - - 101 ds_t dual slope pwm per bottom top 110 ds_tb dual slope pwm per bottom top and bottom 111 ds_b dual slope pwm per bottom bottom bit 76543210 +0x02 - - - - cmpd cmpc cmpb cmpa ctrlc read/write r r r r r/w r/w r/w r/w initial value00000000
151 8077b?avr?06/08 xmega a 13.12.4 ctrld - control register d ? bit 7:5 ? evact[2:0]: event action these bits define the event action the ti mer will perform on an event according to table 13-5 on page 151 . the evsel setting will decide which event source or sources that have the control in this case. selecting the any of the capture event acti on changes the behavior of the ccx registers and related status and control bits to be used as fo r capture. the er ror status flag (errif) will in this configuration indicate a buffer overflow. ? bit 4 ? evdly: timer delay event when this bit is set, the selected event source is delayed by one peripheral clock cycle. this fea- ture is intended for 32-bit input capture operati on. adding the event delay is necessary for compensating for the carry propagation delay th at is inserted when cascading two counters via the event system. ? bit 3:0 ? evsel[3:0]:ti mer event source select these bits select the event channel source for the timer/counter. for the selected event chan- nel to have any effect on the behavior of the timer/counter the event action bits (evact) must be set according to table 13-6 . bit 76543210 +0x03 evact[2:0] evdly evsel[3:0] ctrld read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 13-5. timer event action selection evact[2:0] group configuration event action 000 off none 001 capt input capture 010 updown externally controlled up/ down count 011 qdec quadrature decode 100 restart reserved 101 frq frequency capture 110 pw pulse width capture 111 reserved
152 8077b?avr?06/08 xmega a 13.12.5 ctrle - control register e ? bit 7:2 ? res: reserved these bits are unus ed and reserved for future use. for compatibility with futu re devices, always write these bits to zero when this register is written. ? bit 1 - dthm: dead-time hold mode: setting this bit enables the dead-time hold mode. in this mode of operation the counter is halted during the inserted dead time. this featur e is only available for timer/counters that include the awex extension. ? bit 0 - bytem: byte mode: enabling the byte mode, sets the timer/counter in byte (8-bit) mode. setting this bit will disable the update of the temporary register (temp) when any of the 16-bit timer/counter registers are accessed. in addition th e upper byte of the counter (cnt) r egister will be set to zero after each counter clock. 13.12.6 intctrla - interrupt enable register a table 13-6. timer event source selection evsel[3:0] group configuration event source 0000 off none 0001 reserved 0010 reserved 0011 reserved 0100 reserved 0101 reserved 0110 reserved 0111 reserved 1xxx chn event channel n, n={0,...,7} bit 76543210 +0x04 - - - - - - dthm bytem ctrle read/write r r r r r r r/w r/w initial value00000000 bit 76543210 +0x06 ----errintlvl[1:0]ovfintlvl[1:0]intctrla read/writerrrrr/wr/wr/wr/w initial value00000000
153 8077b?avr?06/08 xmega a ? bit 7:4 - res: reserved these bits are unus ed and reserved for future use. for compatibility with futu re devices, always write these bits to zero when this register is written. ? bit 3:2 - errintlvl[1:0]:timer error interrupt level these bits enable the timer error interrupt and select the interrupt level as described in ?inter- rupts and programmable multi-level interrupt controller? on page 108 . ? bit 1:0 - ovfintlvl[1:0]:timer overflow/underflow interrupt level these bits enable the timer overflow/underflow interrupt and select the interrupt level as described in ?interrupts and programmable multi-level interrupt controller? on page 108 . 13.12.7 intctrlb - interrupt enable register b ? bit 7:0 - ccxintlvl[1:0] - compare or capture x interrupt level: these bits enable the timer compare or capture interrupt and select the interrupt level as described in ?interrupts and programmable multi-level interrupt controller? on page 108 . 13.12.8 ctrlfclr/ctrlfset - st atus register a clear/set this register is mapped into two i/o memory locations, one for clearing (ctrlxclr) and one for setting the register bits (ctrlxset) when writte n. both memory locations yield the same result when read. the individual status bit can be set by writing a one to its bit location in ctrlxset, and cleared by writing a one to its bit location in ctrlxclr. this each bit to be set or cleared without using of a read-modify-write operation on a single register. bit 76543210 +0x07 ccdintlvl[1:0] cccintlvl[1:0] ccbintlvl[1:0] ccaintlvl[1:0] intctrlb read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 +0x08 - - - - cmd[1:0] lupd dir ctrlfclr read/writerrrrrrr/wr/w initial value00000000 bit 76543210 +0x09 - - - - cmd[1:0] lupd dir ctrlfset read/write r r r r r/w r/w r/w r/w initial value00000000
154 8077b?avr?06/08 xmega a ? bit 7:4 - res: reserved these bits are unus ed and reserved for future use. for compatibility with futu re devices, always write these bits to zero when this register is written. ? bit 3:2 - cmd[1:0]: timer/counter command these command bits can be used for software control of update, restart, and reset of the timer/counter. the command bits are always read as zero. ? bit 1 - lupd: lock update: when this bit is set no update of the buffered registers is performed, even though an update condition has occurred. locking the update ensures that all buffers, including dti buffers, are valid before an update is performed. this bit has no effect when input capture operation is enabled. ? bit 0 - dir: counter direction: when zero, this bit indicates that the counter is counting up (incrementing). a one indicates that the counter is in down counting (decrementing) state. normally this bit is controlled in hardware by the waveform generation mode, or by event actions, but this bit can also be changed from software. 13.12.9 ctrlgclr/ctrlgset - status register b clear/set refer to section ?ctrlfclr/ctrlfset - status register a clear/set? on page 153 for infor- mation on how to access this type of status register. ? bit 7:5 - res: reserved these bits are unus ed and reserved for future use. for compatibility with futu re devices, always write these bits to zero when this register is written. ? bit 4:1 - ccxbv: compare or capture x buffer valid these bits are set when a new value is written to the corresponding ccxbuf register. these bits are automatically cleared on an update condition. note that when input capture operation is used, this bit is set on capture event and cleared if the corresponding ccxif is cleared. table 13-7. command selections cmd group configuration command action 00 none none 01 update force update 10 restart force restart 11 reset force hard reset (ignored if t/c is not in ?off?state) bit 76543210 +0x0a/ +0x0b - - - ccdbv cccbv ccbbv ccabv perbv ctrlgclr/set read/write r r r r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0
155 8077b?avr?06/08 xmega a ? bit 0 - perbv: period buffer valid this bit is set when a new value is written to the perbuf register. this bit is automatically cleared on an update condition. 13.12.10 intflags - interrupt flag register ? bit 7:4 - ccxif: compare or capture channel x interrupt flag the compare or capture interrupt flag (ccxif) is set on a compare match or on an input cap- ture event on the corresponding cc channel. for all modes of operation except for capture the ccxif will be set when a compare match occurs between the count register (cnt) and the corresponding compare register (ccx). the ccxif is automatically cleared when the corresponding interrupt vector is executed. for input capture operat ion the ccxif will be set if the co rresponding compar e buffer contains valid data (i.e. when ccxbv is se t). the flag will be cleared when the ccx register is read. exe- cuting the interrupt vector will in this mode of operation not clear the flag. the flag can also be cleared by writing a one to its bit location. the ccxif can be used for requesting a dma transfer. a dma read or write access of the corre- sponding ccx or ccxbuf will then clear the ccxif and rele ases the request. ? bit 3:2 - res: reserved these bits are reserved and will always be read as zero. for compatibility with future devices, always write these bits to zero when this register is written. ? bit 1 - errif: error interrupt flag the errif is set on multiple occasions depending on mode of operation. in frq or pwm waveform generation mode of ope ration the errif is set on a fault detect con- dition from the fault protection feature in the awex extention. for timer/counters which do not have the awex extention available, this flag is never set in frq or pwm waveform generation mode. for capture operation the errif is set if a buffer overflow occurs on any of the cc channels. for event controlled qdec operation the errif is set when an incorrect index signal is given. the errif is automatically cleared when the corresponding interrupt vector is executed. the flag can also be cleared by writing a one to its bit location. ? bit 0 - ovfif: overflow/underflow interrupt flag the ovfif is set either on a top (overflow) or bottom (underflow) condition depending on the wgmode setting. the ovfif is automatically cleared when the corresponding interrupt vector is executed. the flag can also be cl eared by writing a one to its bit location. the ovfif can also be used for requesting a dma transfer. a dma write access of cnt, per, or perbuf will then clear the ovfif bit. bit 76543210 +0x0c ccdif cccif ccbif ccaif - - errif ovfif intflags read/write r/w r/w r/w r/w r r r/w r/w initial value 0 0 0 0 0 0 0 0
156 8077b?avr?06/08 xmega a 13.12.11 temp - temporary register for 16-bit access the temp register is used for single cycle 16-bit access to t he 16-bit timer/counter registers from the cpu. the dma controller has a separate temporary storage register. there is one com- mon temp register for all the 16-bit timer/counter registers. for more details refer to ?accessing 16-bits registers? on page 12 . 13.12.12 cnth - counter register h the cnth and cntl register pair represents t he 16-bit value cnt. cnt contains the 16-bit counter value in the timer/counter. the cpu and dma write access has priority over count, clear, or reload of the counter. for more details on reading and writing 16-bit register refer to ?accessing 16-bits registers? on page 12 . ? bit 7:0 - cnt[15:8] these bits holds the 8 msb of the 16-bit counter register. 13.12.13 cntl - counter register l ? bit 7:0 - cnt[7:0] these bits holds the 8 lsb of the 16-bit counter register. 13.12.14 perh - period register h the perh and perl register pair represents t he 16-bit value per. per contains the 16-bit top value in the timer/counter. ? bit 7:0 - per[15:8] these bits holds the 8 msb of the 16-bit period register. bit 76543210 +0x0f temp[7:0] temp read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 +0x21 cnt[15:8] cnth read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 +0x20 cnt[7:0] cntl read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 +0x27 per[15:8] perh read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value11111111
157 8077b?avr?06/08 xmega a 13.12.15 perl - period register l ? bit 7:0 - per[7:0] these bits holds the 8 lsb of the 16-bit period register. 13.12.16 ccxh - compare or capture register n h the ccxh and ccxl register pair represents the 16-bit value ccx. these 16-bit registers have two functions dependent of mode of operation. for capture opera- tion these registers constitute the second buffer level and access point for the cpu and dma. for compare operation these registers are all continuously compared to the counter value. nor- mally the outputs form the comparators are then used for generating waveforms. ccx are updated with the buffer value from the corresponding ccxbuf register when an update condition occurs. ? bit 7:0 - ccx[15:8] these bits holds the 8 msb of the 16-bit compare or capture register. 13.12.17 ccxl - compare or capture register n l ? bit 7:0 - ccx[7:0] these bits holds the 8 lsb of the 16-bit compare or capture register. 13.12.18 perbufh - timer/counter period buffer h the perbufh and perbufl register pair repres ents the 16-bit value perbuf. this 16-bit register serves as the buffer for the period register (per). accessing this register using cpu or dma will affect the perbufv flag. bit 76543210 +0x26 per[7:0] perl read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 1 1 1 1 1 1 1 1 bit 76543210 ccx[15:8] ccxh read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 ccx[7:0] ccxl read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000
158 8077b?avr?06/08 xmega a ? bit 7:0 - perbuf[15:8] these bits holds the 8 msb of the 16-bit period buffer register. 13.12.19 perbufl - timer/counter period buffer l ? bit 7:0 - perbuf[7:0] these bits holds the 8 lsb of the 16-bit period buffer register. 13.12.20 ccxbufh - compare or capture x buffer register h the ccxbufh and ccxbufl register pair represents the 16-bit value ccxbuf. this 16-bit reg- isters serve as the buffer for the associated co mpare or capture registers (ccx). accessing any of these register using cp u or dma will affect the corr esponding ccxbv status bit. ? bit 7:0 - ccxbuf[15:8] these bits holds the 8 msb of the 16-bit compare or capture buffer register. 13.12.21 ccxbufl - compare or capture x buffer register l ? bit 7:0 - ccxbuf[7:0] these bits holds the 8 lsb of the 16-bit compare or capture buffer register. bit 76543210 +0x37 perbuf[15:8] perbufh read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 1 1 1 1 1 1 1 1 bit 76543210 +0x36 perbuf[7:0] perbufl read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value11111111 bit 76543210 ccxbuf[15:8] ccxbufh read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 ccxbufx[7:0] ccxbufl read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000
159 8077b?avr?06/08 xmega a 13.13 register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page +0x00 ctrla clksel[3:0] 149 +0x01 ctrlb ccden cccen ccb en ccaen - wgmode[2:0] 149 +0x02 ctrlc - - - - cpmd cpmc cpmb cpma 150 +0x03 ctrld evact[2:0] evdly evsel[3:0] 151 +0x04 ctrle - - - - - dthm bytem 152 +0x05 reserved - - - - - - - - +0x06 intctrla - - - - errintlvl[1:0] ovintlvl[1:0] 152 +0x07 intctrlb cccintlvl[1:0] cccintlvl[ 1:0] ccbintlvl[1:0] ccaintlvl[1:0] 152 +0x08 ctrlfclr - - - - cmd[1:0] lupd dir 153 +0x09 ctrlfset - - - - cmd[1:0] lupd dir 154 +0x0a ctrlgclr - - - ccdbv ccc bv ccbbv cca bv perbv 154 +0x0b ctrlgset - - - ccdbv ccc bv ccbbv cca bv perbv 154 +0x0c intflags ccdif cccif ccbif ccaif - - errif ovfif 155 +0x0d reserved - - - - - - - - +0x0e reserved - - - - - - - - +0x0f temp temporary register (for 16-bit access) 156 +0x10 to +0x1f reserved - - - - - - - - +0x20 cntl timer/counter count register low byte 156 +0x21 cnth timer/counter count register highbyte 156 +0x22 to +0x25 reserved - - - - - - - - +0x26 perl timer/counter period register low byte 157 +0x27 perh timer/counter period register low byte 156 +0x28 ccal compare or capture register a low byte 157 +0x29 ccah compare or capture register a high byte 157 +0x2a ccbl compare or capture register b low byte 157 +0x2b ccbh compare or capture register b high byte 157 +0x2c cccl compare or capture register c low byte 157 +0x02d ccch compare or capture register c high byte 157 +0x2e ccdl compare or capture register d low byte 157 +0x2f ccdh compare or capture register d high byte 157 +0x30 to +0x35 reserved - - - - - - - - +0x36 perbufl timer/counter period buffer register low byte 158 +0x37 perbufh timer/counter period buffer register low byte 157 +0x38 ccabufl compare or capture buffer register a low byte 158 +0x39 ccabufh compare or capture buffer register a high byte 158 +0x3a ccbbufl compare or capture buffer register b low byte 158 +0x3b ccbbufh compare or capture bufferregister b high byte 158 +0x3c cccbufl compare or capture buffer register c low byte 158 +0x3d cccbufh compare or capture buffer register c high byte 158 +0x3e ccdbufl compare or capture buffer register d low byte 158 +0x3f ccdbufh compare or capture buffer register d high byte 158
160 8077b?avr?06/08 xmega a 14. awex ? advanced waveform extension 14.1 features ? 4 dead-time insertion (dti) units (8-pin) ? 8-bit resolution ? separate high and low side dead-time setting ? double buffered dead-time ? halts timer during dead-time (optional) ? event controlled fault protection ? single channel multiple output operation (for bldc control) ? double buffered pattern generation ? the hi-resolution timer exte nsion increases pwm/frq r esolution by 2-bits (4x) 14.2 overview the advanced waveform extention (awex) provi des extra features to the timer/counter in waveform generation (wg) modes. the awex enables easy and robust implementation of advanced motor control (ac, bldc, sr, and stepper) and power control applications. figure 14-1. advanced waveform extention and closely related peripherals (grey) as shown in figure 14-1 on page 160 each of the waveform generator outputs from the timer/counter 0 are split into a complimentar y pair of outputs when any awex features is enabled. these output pairs go through a dead-time insertion (dti) unit that enables genera- tion of the non-inverted low side (ls) and inverted high side (hs) of the wg output with dead time insertion between ls and hs switching. the dti output will override the normal port value portx timer/counter 0 awex wg channel a dti channel a wg channel b dti channel b wg channel c dti channel c wg channel d dti channel d port override pattern generation px0 px1 px2 px3 px4 px5 px6 px7 inven inven inven inven inven inven inven inven event system fault protection
161 8077b?avr?06/08 xmega a according to the port override setting. optionally the final output can be inverted by using the invert i/o (inven) bit setting for the port pin (pxn). the pattern generation unit can be used to generate a synchronized bit pattern on the port it is connected to. in addition, the waveform generator output from the compare channel a can be distributed to and override all the port pins. when the pattern generator unit is enabled the dti unit is bypassed. the fault protection unit is connected to the even t system, enabling any event to trigger a fault condition that will disable the awex output. 14.3 port override common for all the timer/counter extensions is the port override logic. figure 14-2 on page 162 shows a schematic diagram of the port override logic. when the dead-time enable (dtienx) bit is set the timer/counter extension takes control over the pin pair for the corresponding channel. given this condition the output override enable (ooe) bits takes control over the ccxen. note that timer/coun ter 1 (tcx1) can still be used even when dti channels a, b, and d are enabled.
162 8077b?avr?06/08 xmega a figure 14-2. timer/counter extensions and port override logic portx0 ooe0 ccena dtiena invx0 portx1 ooe1 ccenb invx1 px0 px1 channel a dti ls hs oc0a oc0b oclsa ochsa wg 0a wg 0b wg 0a cwcm portx2 ooe2 ccenc dtienb invx2 portx3 ooe3 ccend invx3 px2 px3 channel b dti ls hs oc0c oc0d oclsb ochsb wg 0c wg 0d portx4 ooe4 ccena dtienc invx4 portx5 ooe5 ccenb invx5 px4 px5 channel c dti ls hs oc1a oc1b oclsc ochsc wg 1a wg 1b portx6 ooe6 dtiend invx6 portx7 ooe7 invx7 px6 px7 channel d dti ls hs oclsd ochsd wg 0b wg 0d wg 0c "0" "0"
163 8077b?avr?06/08 xmega a 14.4 dead time insertion the dead time insertion (dti) unit enables generation of ?off? time where both the non-inverted low side (ls) and inverted high side (hs) of the wg output is low. this ?off? time is called dead-time, and dead-time insertion ensure that the ls and hs does not switch simultaneously. the dti unit consists of four equal dead time generators, one for each of the capture or com- pare channel in timer/counter 0. figure 14-3 on page 163 shows the block diagram of one dead time generator. the dead time registers that define the number of peripheral clock cycles the dead time is going to last, are common for all four channels. the high side and low side can have independent dead time setting and the dead time registers are double buffered. figure 14-3. dead time generator block diagram as shown in figure 14-4 on page 164 , the 8-bit dead time counter (dti_cnt) is decremented by one for each peripheral clock cycle until it re aches zero. a non-zero co unter value will force both the low side and high side outputs into their ?off? state. when a change is detected on the wg output, the dead time counter is reloaded with the dtx register value according to the edge of the input. positive edge initiates a counter reload of the dtls register and a negative edge a reload of dths register. dead time generator edge detect v v dq = 0 dtlsbuf dtils dthsbuf dtihs wg output "dtls" (to port) "dths" (to port) counter ("dti_cnt") e load
164 8077b?avr?06/08 xmega a figure 14-4. dead time generator timing diagram 14.5 pattern generation the pattern generator extension reuses the dti registers to produce a synchronized bit pattern on the port it is connected to. in addition, the waveform generator output from cc channel a (cca)) can be distributed to and override all th e port pins. these features are primarily intended for handling the commutation sequence in bldc and stepper motor applications. figure 14-5. pattern generator block diagram a block diagram of the pattern generator is shown in figure 14-5 on page 164 . for each port pin where the correspo nding ooe bit is set the multiple xer will output the waveform from cca. as for all other types of the timer/counter double-buffered registers the register update is syn- chronized to the update condition set by the waveform generation mode. if the synchronization provided is not required by t he application, the application code can simply access the dtioe and port x registers directly. the pins direction must be set for any output from the pattern generator to be visible on the port. "dti_cnt" "wg output" "dtls" "dths" t dtils t dtihs t t p timer/counter 0 (tcx0) v v dtibls dtioe[7:0] dtibhs portx[7:0] cca wg output update en en 1 to 8 expand px[7:0]
165 8077b?avr?06/08 xmega a 14.6 fault protection the fault protection feature enables fast and deterministic action when a fault is detected. the fault protection is event controlled, thus any even t from the event system can be used to trigger a fault action. when the fault protection is enabled an incoming event from any of the selected event channel can trigger the event action. each event channel can be separately enabled as fault protection input, and the spec ified event channels will be ored together allowing multiple event sources top be used for fault protection at the same time. 14.6.1 fault actions two different even actions can be selected: ? the clear override enable action will clear th e output override enab le register (outoven) and disable the output override on all timer/counter outputs. the result is that the in the output will be as set by the port pin configuration. ? the direction clear action will clear the direction (dir) register in the associated port, setting all port pins as tri-stated inputs. when a fault is detected the fault detection flag is set, and the timer/counter?s error interrupt flag is set and the optional interrupt is generated. from the event occurs in one peripherals until the fault protection triggers the event action, there is maximum two peripheral clock cycles. the fault protec tion is fully independent of the cpu and dma, but it requires the peripheral clock to run. 14.6.2 fault restore modes after a fault, that is when the fault condition is no longer active, it is selectable how the awex and timer/counter can return from fault state and restore with normal operation. two different modes are available: ? in latched mode the waveform out put will remain in the fault stat e until the faul t condition is no longer active and the fault detect flag has been cleared by software. when both of these conditions are met, the waveform output will retu rn to normal operation at the next update condition. ? in cycle-by-cycle mode the waveform output will remain in the fault state until the fault condition is no longer active. when this condition is met, the waveform output will return to normal operation at the next update condition. when entering fault state and the clear override enable action is selected, the outoven[7:0] bits are reassigned a value on the next update c ondition. in pattern generation mode the reg- ister is restored wit h the value in the dtlsbuf register. otherwise the register bits are restored according to the enabled dti channels. when entering fault state and direction clear action is select is set, corresponding dir[7:0] bits is restored with the value in the dtlsbuf register in pattern generation mode and for the pin pairs corresponding to enabled dti channels otherwise. the update condition used to restore the normal operation is the same update as in the timer/counter. 14.6.3 change protection to avoid unintentional changes in the fault protection setup all the control registers in the awex extension can be protected by writing the corr esponding lock bit advanced waveform extension
166 8077b?avr?06/08 xmega a lock register. for more details refer to ?io memory protection? on page 24 and ?awexlock ? advanced waveform extension lock register? on page 38 . when the lock bit is set, the control register a, the output override enable register and the fault dedec.tion event mask register cannot be changed. to avoid unintentional changes in the fault event setup it is possible to lock the event system channel configuration by writing the corres ponding event system lock register. for more details refer to ?io memory protection? on page 24 and ?evsyslock ? event system lock register? on page 37 . 14.6.4 on-chip debug when fault detection is enabled an ocd system receives a break request from the debugger, this will by default function as a fault sour ce. when an ocd break r equest is received, the awex and corresponding timer/counter will enter fa ult state and the specified fault action(s) will be performed. after the ocd exits from the break condition, normal operation will be started again. in cycle-by- cycle mode the waveform output will start on the fi rst update cond ition after exit from break, and in latched mode, the fault condition flag must be cleared in software before the output will be restored. this feature guarantees that the output waveform enters a safe state during break. it is possible to disable this feature. 14.7 register description 14.7.1 ctrl - control register ? bit 7:6 - res - reserved these bits are unus ed and reserved for future use. for compatibility with futu re devices, always write these bits to zero when this register is written. ? bit 5 - pgm: pattern generation mode setting this bit enables the pattern generation mode if set. this will over ride the dti if enabled, and the pattern generation reuses the dead-time registers for storing the pattern. ? bit 4 - cwcm: common waveform channel mode if this bit is set cc channel a waveform output will be used as input fo r all the dead-time genera- tors. cc channel b, c, and d waveforms will be ignored. ? bit 3:0 - dticcxen: dead-time insertion ccx enable setting these bits enables the de ad time generator for the corr esponding cc channel. this will override the timer/counter waveform outputs. bit 76543210 +0x00 - - pgm cwcm dticcden dti cccen dticcben dticcaen ctrl read/write r r r/w r/w r/w r/w r/w r/w initial value00000000
167 8077b?avr?06/08 xmega a 14.7.2 fdemask - fault detect event mask register ? bit 7:0 - fdevmask[7:0]: fault detect event mask these bits enables the corresponding event channel as fault condition input source. event from all event channels will be ored to gether allowing mult iple sources to be used for fault detection at the same time. when a fault is detected the fault detect flag fdf is set and the fault detect action (fdact) will be performed. 14.7.3 fdctrl - fault de tection control register ? bit 7:5 - res - reserved these bits are unus ed and reserved for future use. for compatibility with futu re devices, always write these bits to zero when this register is written. ? bit 4 - fddbd: fault detection on debug break detection by default, when this bit is cleared and the fault protection is enabled, and ocd break request is treated as a fault. when this bit is set, an oc d break request will not tr igger a fault condition. ? bit 3 - res - reserved this bit is unused and reserved fo r future use. for comp atibility with future devices, always write this bit to zero when this register is written. ? bit 2- fdmode: fault detection restart mode this bit sets the fault protection restart mode. when this bit is cleared latched mode is use, and when this is set cycle-by-cycle mode is used. in latched mode the wave form output will remain in the fault state until the fault condition is no longer active and the fdf has been cleared by software. when both of these conditions are met, the waveform output will re turn to normal ope ration at the next update condition. in cycle-by-cycle mode the waveform output will rema in in the fault state un til the faul t condition is no longer active. when this condition is met, the waveform output will re turn to normal opera- tion at the next update condition . ? bit 1:0 - fdact[1:0]: fault detection action these bits define the action performed if a fault condition is detected, according to table 14-1 . bit 76543210 +0x02 fdevmask[7:0] fdemask read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 +0x03 - - - fddbd - fdmode fdact[1:0] fdctrl read/write r r r r/w r r/w r/w r/w initial value00000000
168 8077b?avr?06/08 xmega a 14.7.4 status - status register ? bit 7:3 - res: reserved these bits are reserved and will always be read as zero. for compatibility with future devices, always write these bits to zero when this register is written. ? bit 2 - fdf: fault detect flag this flag is set when a fault detect condition is detected, i.e. when an event is detected on one of the event channels enabled by the fdevmask. this flag is cleared by writing a one to its bit location. ? bit 1 - dthsbufv: dead-time high side buffer valid if this bit is set the correspondi ng dt buffer is written and contai ns valid data that will be copied into the dtls register on the update condition. if this bit is zero no action will be taken. the connected timer/counter?s lock update (lupd) flag also affects the update for dead time buffers. ? bit 0 - dtlsbufv: dead-time low side buffer valid if this bit is set the correspondi ng dt buffer is written and contai ns valid data that will be copied into the dths register on the up date condition. if this bit is zero no action will be taken. note that the connected timer/counter unit's lock update (lupd) flag also affects the update for dead time buffers. 14.7.5 dtboth - dead-time concurrent write to both sides table 14-1. fault actions fdact[1:0] group configuration description 00 none none (fault protection disabled) 01 clearoe clear all override enable (outoven) bits, i.e. disable the output override. 11 cleardir clear all direction (dir) bits, which correspond to enabled dti channel(s), i.e. tri-state the outputs bit 76543 2 1 0 +0x04 - - - - - fdf dthsbufv dtlsbufv status read/write r r r r r r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 +0x06 dtboth[7:0] dtboth read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000
169 8077b?avr?06/08 xmega a ? bit 7:0 - dtboth: dead-time both sides writing to this register will upda te both dths and dtls registers at the same time (i.e. at the same i/o write access). 14.7.6 dtbothbuf - dead-time concurrent write to both sides buffer ? bit 7:0 - dtbothbuf: dead-time both sides buffer writing to this memory loca tion will update both dthsbuf and dtlsbuf registers at the same time (i.e. at the same i/o write access). 14.7.7 dtls - dead-time low side register ? bit 7:0 - dtls: dead-time low side this register holds the number of peripheral clock cycles for the dead-time low side. 14.7.8 dths - dead-time high side register ? bit 7:0 - dths: dead-time high side this register holds the number of peripheral clock cycles for the dead-time high side. 14.7.9 dtlsbuf - dead-time low side buffer register ? bit 7:0 - dtlsbuf: dead-time low side buffer this register is the buffer for the dtls register. if double buffering is used, valid contents in this register is copied to the dtls register on an update condition. bit 76543210 +0x07 dtbothbuf[7:0] dtbothbuf read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 +0x08 dtls[7:0] dtls read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 +0x09 dths[7:0] dths read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 +0x0a dtlsbuf[7:0] dtlsbuf read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000
170 8077b?avr?06/08 xmega a 14.7.10 dthsbuf - dead-time high side buffer register ? bit 7:0 - dthsbuf: dead-time high side buffer this register is the buffer for the dths register. if double buffering is used , valid contents in this register is copied to the dths register on an update condition. 14.7.11 outoven - output override enable register note: 1. can only be written if the fault detect flag (fdf) is zero. ? bit 7:0 - outoven[7:0]: output override enable these bits enable override of corresponding port output register (i.e. one-to-one bit relation to pin position). the port direction is not overridden bit 76543210 +0x0b dthsbuf[7:0] dthsbuf read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 +0x0c outoven[7:0] outoven read/write r/w (1) r/w (1) r/w (1) r/w (1) r/w (1) r/w (1) r/w (1) r/w (1) initial value00000000
171 8077b?avr?06/08 xmega a 14.8 register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page +0x00 ctrla - - pgm cwcm dtiend dtienc dtienb dtiena 166 +0x01 reserved - - - - - - - - +0x02 fdemask fdevmask[7:0] 167 +0x03 fdctrl - - - fddbd - fdmode fdact[1:0] 167 +0x04 status - - - - - fdf dtbhsv dtblsv 168 +0x05 reserved - - - - - - - - +0x06 dtbs dead-time both sides 169 +0x07 dtbufbs dead-time buffer both sides 168 +0x08 dtls dead-time low sides 168 +0x09 dths dead-time high sides 169 +0x0a dtbufls dead-time buffer low sides 168 +0x0b dtbufhs dead-time buffer high sides 168 +0x0c outoven outoven[7:0]
172 8077b?avr?06/08 xmega a 15. hi-res - high r esolution extension 15.1 features ? increases waveform generator resolution by 2-bits (4x) ? supports frq, single and dual-slope pwm operation ? supports dead-time insertion (awex) ? supports pattern generation (awex) 15.2 overview the hi-resolution (hi-res) extent ion is able to increase the resolution of the waveform genera- tion output by 4. 15.3 register description 15.3.1 ctrla - hi-res control register a ? bit 7:2 - res: reserved these bits are reserved and will always be read as zero. for compatibility with future devices, always write these bits to zero when this register is written. ? bit 1:0 - hren[1:0]: hi-resolution enable enables hi-resolution mode for a timer/counter according to table 15-1 . setting one or both hren bits will enable hi-resolution wave form generation output for the entire general purpose i/o port. this means that both timer/counters connected to the same port must enable hi-res if both are used for generating pwm or frq output on pins. 15.4 register summary bit 76543210 +0x00 ------ hren[1:0]ctrla read/writerrrrrrr/wr/w initial value00000000 table 15-1. hi-resolution enable hren[1:0] hi-resolu tion enabled 00 none 01 timer/counter 0 10 timer/counter 1 11 both timer/counters address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page +0x00 ctrla hren[1:0] 172
173 8077b?avr?06/08 xmega a 16. rtc - real time counter 16.1 features ? 16-bit resolution ? selectable clock reference ? 32.768 khz or 1.024 khz ? programmable prescaler ? 1 compare register ? 1 period register ? clear timer on overflow ? optional interrupt/ event on overflow and compare match 16.2 overview the real time counter (rtc) is a 16-bit counter, counting reference clock cycles and giving an event and/or an interrupt request when it reaches a configurable compare and/or top value. the reference clock is typically generated from a high accuracy crystal of 32.768 khz, and the design is optimized for low power consumption. the rt c typically operate in low power sleep modes, keeping track of time and waking up the device at regular intervals. the rtc reference clock may be taken from an 32.768 khz or 1.024 khz input. both an external 32.768 khz crystal oscillator or the 32 khz inte rnal rc oscillator can be selected as clock source. for details on reference clock selection to the rtc refer to section 7.9.4 ?rtcctrl - rtc control register? on page 77 in the clock system section. the rtc has a programmable prescaler to scale down the reference clock before it reaches the counter. there are two ways of generating interrupt requests and even ts. the rtc will give a compare interrupt request and/or event when the counter value equals the compare register value. the rtc will give an overflow interrupt request and/or event when the counter value equals the period register value. the overflow will also reset the counter value to zero.
174 8077b?avr?06/08 xmega a figure 16-1. real time counter overview. 16.3 register description 16.3.1 ctrl - real time counter control register ? bits 7:3 - res: reserved these bits are unus ed and reserved for future use. for compatibility with futu re devices, always write these bits to zero when this register is written. ? bits 2:0 - prescaler[2:0]: rtc clock prescaling factor these bits define the prescaling factor for the rtc clock before the counter according to table 16-1 on page 174 . 10-bit prescaler 16-bit counter 16-bit period 16-bit compare = = overflow compare match 1 khz 32 khz bit 76543210 +0x00 - - - - - prescaler[2:0] ctrl read/write r r r r r r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 16-1. real time counter clock prescaling factor prescaler[2:0] group configuration rtc clock prescaling 000 off no clock source, rtc stopped 001 div1 rtc clock / 1 (no prescaling) 010 div2 rtc clock / 2 011 div8 rtc clock / 8 100 div16 rtc clock / 16 101 div64 rtc clock / 64 110 div256 rtc clock / 256 111 div1024 rtc clock / 1024
175 8077b?avr?06/08 xmega a 16.3.2 status - real time counter status register ? bits 7:1 - res: reserved these bits are reserved and will always be read as zero. for compatibility with future devices, always write these bits to zero when this register is written. ? bit 0 - syncbusy: rtc synchronization busy flag this bit is set when the cnt, ctrl or comp register is busy synchronizing between the rtc clock and system clock domains. 16.3.3 intctrl - real time counter interrupt control register ? bits 7:4 - res: reserved these bits are unus ed and reserved for future use. for compatibility with futu re devices, always write these bits to zero when this register is written. ? bits 3:2 - compintlvl[1:0]: rtc compare match interrupt enable these bits enable the rtc overflow interrupt and select the interrupt level as described in ?interrupts and programmable multi-level interrupt controller? on page 108 . the enabled inter- rupt will trigger when the compif in the intflags register is set. ? bits 1:0 - ovfintlvl[1:0]: rtc overflow interrupt enable these bits enable the rtc overflow interrupt and select the interrupt level as described in ?interrupts and programmable multi-level interrupt controller? on page 108 . the enabled inter- rupt will trigger when the ovfif in the intflags re gister is set. bit 7654321 0 +0x01 -------syncbusystatus read/writerrrrrrrr/w initial value0000000 0 bit 76543210 +0x02 - - - - compintlvl[1:0] ovfintlvl[1:0] intctrl read/write r r r r r/w r/w r/w r/w initial value00000000
176 8077b?avr?06/08 xmega a 16.3.4 intflags - rtc interrupt flag register ? bits 7:2 - res: reserved these bits are reserved and will always be read as zero. for compatibility with future devices, always write these bits to zero when this register is written. ? bit 1 - compif: rtc compare match interrupt flag this flag is set on the next count after a co mpare match condition occurs. the flag is cleared automatically when rtc compare match interrupt vector is executed. the flag can also be cleared by writing a one to its bit location. ? bit 0 - ovfif: rtc overflow interrupt flag this flag is set on the count after a overflow condition occurs. the flag is cleared automatically when rtc overflow interrupt vector is executed. the flag can also be cleared by writing a one to its bit location. 16.3.5 temp - rtc temporary register ? bits 7:0 - temp[7:0]: real time counter temporary register this register is used for 16-bit access to the counter value, compare value and top value regis- ters. the low byte of the 16-bit register is stored here when it is written by the cpu. the high byte of the 16-bit register is stored when low byte is read by the cpu. for more details refer to ?accessing 16-bits registers? on page 12 . 16.3.6 cnth - real time counter register h the cnth and cntl register pair represents th e 16-bit value cnt. cnt counts positive clock edges on the prescaled rtc clock. reading and writ ing 16-bit values require special attention, refer to ?accessing 16-bits registers? on page 12 for details. due to synchronization between rtc clock and the system clock domains, there is a latency of two rtc clock cycles from updating the register until this has an effect. application software needs to check that the syncbusy flag in the ?status - real time counter status register? on page 175 is cleared before writing to this register. bit 76543210 +0x03 ------compifovfifintflags read/writerrrrrrr/wr/w initial value00000000 bit 76543210 +0x04 temp[7:0] temp read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 +0x09 cnt[15:8] cnth read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000
177 8077b?avr?06/08 xmega a ? bits 7:0 - cnt[15:8]: real time counter value high byte these bits hold the 8 msb of the 16-bit real time counter value. 16.3.7 cntl - real time counter register l ? bits 7:0 - cnt[7:0]: real time counter value low byte these bits hold the 8 lsb of the 16-bit real time counter value. 16.3.8 perh - real time counter period register high the perh and perl register pair represents the 16-bit value per. per is constantly com- pared with the counter value ( cnt). a match will set the ovfif in the intflags register and clear cnt. reading and writing 16-bit val ues require special attention, refer to ?accessing 16- bits registers? on page 12 for details. due to synchronization between rtc clock and the system clock domains, there is a latency of two rtc clock cycles from updating the register until this has an effect. application sw needs to check that the syncbusy flag in the ?status - real time counter status register? on page 175 is cleared before writing to this register. ? bits 7:0 - per[15:8]: real time counter period high byte these bits hold the 8 msb of the 16-bit rtc top value. 16.3.9 perl - real time counter period register l ? bits 7:0 - per[7:0]: real time counter period low byte these bits hold the 8 lsb of the 16-bit rtc top value. bit 76543210 +0x08 cnt[7:0] cntl read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 +0x0b per[15:8] perh read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value11111111 bit 76543210 +0x0a per[7:0] perl read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 1 1 1 1 1 1 1 1
178 8077b?avr?06/08 xmega a 16.3.10 comph - real time counter compare register h the comph and compl register pair represent the 16-bit value comp. comp is constantly compared with the counter valu e (cnt). a compare match will set the compif in the intflags register. reading and writing 16-bit values require special attention, refer to ?access- ing 16-bits registers? on page 12 for details. due to synchronization between rtc clock and the system clock domains, there is a latency of two rtc clock cycles from updating the register until this has an effect. application sw needs to check that the syncbusy flag in the ?status - real time counter status register? on page 175 is cleared before writing to this register. if the comp value is higher than the per value, no rtc compare match interrupt requests or events will ever be generated. ? bits 7:0 - comp[15:8]: real time counter compare register high byte these bits hold the 8 msb of the 16-bit rtc compare value. 16.3.11 compl - real time counter compare register l ? bits 7:0 - comp[7:0]: real time counter compare register low byte these bits hold the 8 lsb of the 16-bit rtc compare value. bit 76543210 +0x0d comp[15:8] comph read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 +0x0c comp[7:0] compl read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000
179 8077b?avr?06/08 xmega a 16.4 register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page +0x00 ctrl - - - - - prescaler[2:0] 174 +0x01 status - - - - - - - syncbusy 175 +0x02 intctrl - - - - compintlvl[1:0] ovfintlvl[1:0] 175 +0x03 intflags - - - - - - compif ovfif 176 +0x04 temp temp[7:0] 176 +0x08 cntl cnt[7:0] 176 +0x09 cnth cnt[15:8] 177 +0x0a perl per[7:0] 177 +0x0b perh per[15:8] 177 +0x0c compl comp[7:0] 178 +0x0d comph comp[15:8] 178
180 8077b?avr?06/08 xmega a 17. twi ? two wire interface 17.1 features ? fully independent master and slave operation ? multi-master, single master, or slave only operation ? phillips i 2 c compliant ? smbus compliant ? 100 khz and 400 khz support at low system clock frequencies ? slew-rate limited output drivers ? input filter provides noise suppression ? 7-bit, and general call address recognition in hardware ? 10-bit addressing supported ? optional software address recognition prov ides unlimited number of slave addresses ? slave can operate in all sleep modes, including power down ? support for arbitration between start/ repeated start and data bit (smbus) ? slave arbitration allows support for address resolve protocol (arp) (smbus) 17.2 overview the two wire interface (twi) is bi-directi onal 2-wire bus communication, which is i 2 c and smbus compliant. a device connected to the bus must act as a mast er or slave.the master initiates a data transac- tion by addressing a slave on the bus, and telling whether it wants to transmit or receive data. one bus can have several masters, and an arbitration process handles priority if two or more masters try to transmit at the same time. the twi module in xmega implements both master and slave functionality. the master and slave functionality are separated from each other and can be enabled separately. they have separate control and status register, and separa te interrupt vectors. arbi tration lost, errors, colli- sion and clock hold on the bus will be detected in hardware and indicated in separate status flags available in both master and slave mode. the master module contains a baud rate generator for flexible clock generation. both 100 khz and 400 khz bus frequency at low system clock speed is supported. quick command and smart mode can be enabled to auto trigger operations and reduce software complexity. for the slave, 7-bit and general address call rec ognition is implemented in hardware. 10-bit addressing is also supported. the slave logic continues to operate in all sleep modes, including power down. this enables the slave to wake up fr om sleep on twi address match. it is possible to disable the address matching and let this be handled in software instead. this allows the slave to detect and respond to several addresses. smart mode can be enabled to auto trigger operations and reduce software complexity. the twi module includes bus state logic that collects information to detect start and stop conditions, bus collision and bus errors. this is used to de termine the bus st ate (idle, owner, busy or unknown) in master mode. the bus state logic continues to operate in all sleep modes including power down. it is possible to disable the internal twi driver s in the device, and enabling a 4-wire interface for connecting external bus drivers.
181 8077b?avr?06/08 xmega a 17.3 general twi bus concepts the two-wire interface (twi) provides a simple tw o-wire bi-directional bu s consisting of a serial clock line (scl) and a serial data line (sda). the two lines are open collector lines (wired-and), and pull-up resistors (rp) are the only external components needed to drive the bus. the pull-up resistors will provide a high level on the lines when none of the connect ed devices are driving the bus. a constant current source can be used as an alternative to the pull-up resistors. the twi bus is a simple and efficient method of interconnecting multiple devices on a serial bus. a device connected to the bus can be a master or slave, where the master controls the bus and all communication. figure 17-1 illustrates the twi bus topology. figure 17-1. twi bus topology a unique address is assigned to all slave devices connected to the bus, and the master will use this to address a slave and initiate a data transaction. 7-bit or 10-bit addressing can be used. several masters can be connected to the same bus, and this is called a multi-master environ- ment. an arbitration mechanism is provided for resolving bus ownership between masters since only one master device may own the bus at any given time. a device can contain both master and slave logic, and can emulate multiple slave devices by responding to more than one address. a master indicates the start of transaction by issuing a start condition (s) on the bus. an address packet with a slave address (address) and an indication whether the master wishes to read or write data (r/w ), is then sent. after all data packets (data) are transferred, the mas- ter issues a stop condition (p) on the bus to end the transaction. the receiver must acknowledge (a) or not-acknowledge (a ) each byte received. figure 17-2 shows a twi transaction. twi device #1 r p r p r s r s sda scl v cc twi device #2 r s r s twi device #n r s r s note: r s is optional
182 8077b?avr?06/08 xmega a figure 17-2. basic twi transaction diagram topology the master provides the clock signal for the tr ansaction, but a device connected to the bus is allowed to stretch the low level period of the clock to decrea se the clock speed. 17.3.1 electrical characteristics the twi in xmega follows the electr ical specificati ons and timing of i 2 c and smbus. these specifications are not 100% compliant so to ensure correct behavior th e inactive bus timeout period should be set in twi master mode. 17.3.2 start and stop conditions two unique bus conditions are used for marking the beginning (start) and end (stop) of a transaction. the master issues a start condition(s) by indicating a high to low transition on the sda line while the scl line is kept high. the master completes the transaction by issuing a stop condition (p), indicated by a low to high transition on the sda line while scl line is kept high. figure 17-3. start and stop conditions multiple start conditions can be issued during a single transaction. a start condition not directly following a stop condition, are named a repeated start condition (sr). p s address 6 ... 0 r/w ack ack 7 ... 0 data ack/nack 7 ... 0 data sda scl s a a/a r/w address data p a data address packet data packet #0 transaction data packet #1 direction the slave provides data on the bus the master provides data on the bus the master or slave can provide data on the bus sda scl start condition stop condition s p
183 8077b?avr?06/08 xmega a 17.3.3 bit transfer as illustrated by figure 17-4 a bit transferred on the sda line must be stable for the entire high period of the scl line. consequently the sda value can only be changed during the low period of the clock. this is ensured in hardware by the twi module. figure 17-4. data validity combining bit transfers results in the formation of address and data packets. these packets consist of 8 data bits (one byte) with the most sign ificant bit transferred first, plus a single bit not- acknowledge (nack) or acknowledge (ack) response. the addressed device signals ack by pulling the scl line low, and nack by leaving the line scl high during the ninth clock cycle. 17.3.4 address packet after the start condition, a 7-bit address followed by a read/write (r/w ) bit is sent. this is always transmitted by the master. a slave reco gnizing its address will ac k the address by pull- ing the data line low the next scl cycle, while all other slaves should keep the twi lines released, and wait for the next start and address. the 7-bit address, the r/w bit and the acknowledge bit combined is the address packet. only one address packet for each start condition is given, also when 10-bit addressing is used. the r/w specifies the direction of the transaction. if the r/w bit is low, it indicates a master write transaction, and the ma ster will transmit its data afte r the slave has acknowledged its address. opposite, for a master read operation the slave will st art to transmit data after acknowledging its address. 17.3.5 data packet data packets succeed an address packet or another data packet. all data packets are nine bits long, consisting of one data byte and an acknowl edge bit. the direction bit in the previous address packet determines the direction in which the data is transferred. 17.3.6 transaction a transaction is the complete transfer from a start to a stop condition, including any repeated start conditions in between. the twi standard defines three fundamental transac- tion modes: master write, master read, and combined transaction. figure 17-5 illustrates the master write transaction. the master init iates the transaction by issu- ing a start condition (s) followed by an addr ess packet with direction bit set to zero (address+w ). sda scl data valid change allowed
184 8077b?avr?06/08 xmega a figure 17-5. master write transaction given that the slave acknowledges the address, the master can start transmitting data (data) and the slave will ack or nack (a/a ) each byte. if no data packet s are to be transmitted, the master terminates the transaction by issuing a stop condition (p) directly after the address packet. there are no limitations to the number of data packets that can be transferred. if the slave signal a nack to the data, the master must assume that the slave cannot receive any more data and terminate the transaction. figure 17-6 illustrates the master read tr ansaction. the master initia tes the transacti on by issu- ing a start condition followed by an address packet with direct ion bit set to one (adress+r). the addressed slave must acknowledge the address for the master to be allowed to continue the transaction. figure 17-6. master read transaction given that the slave acknowledges the address, the master can start receiving data from the slave. there are no limitations to the number of data packets that can be transferred. the slave transmits the data while the master signals ack or nack after each data byte. the master ter- minates the transfer with a nack before issuing a stop condition. figure 17-7 illustrates a co mbined transaction. a combined transaction consists of several read and write transactions separated by a repeated start conditions (sr). figure 17-7. combined transaction s a a a/a p w address data data address packet data packet transaction n data packets s r a a a address data data p transaction address packet data packet n data packets s a sr a/a r/w data a/a p address data r/w address transaction address packet #1 n data packets m data packets address packet #2 direction direction a
185 8077b?avr?06/08 xmega a 17.3.7 clock and clock stretching all devices connected to the bus are allowed to stretch the low period of the clock to slow down the overall clock frequency or to insert wait states while processing data. a device that needs to stretch the clock can do this by holding/forcing th e scl line low after it de tects a low level on the line. three types of clock stretching can be defined as shown in figure 17-8 . figure 17-8. clock stretching if the device is in a sleep mode and a start co ndition is detected the clock is stretched during the wake-up period for the device. a slave device can slow down the bus frequency by stretching the clock periodically on a bit level. this allows the slave to run at a lower system clock frequency. however, the overall per- formance of the bus will be reduced accordin gly. both the master and slave device can randomly stretch the clock on a byte level basis before and after the ack/nack bit. this pro- vides time to process incoming or prepare outgoing data, or performing other time critical tasks. in the case where the slave is stre tching the clock the master will be forced into a wait-state until the slave is ready and vice versa. 17.3.8 arbitration a master can only start a bus transaction if it has detected that the bus is idle. as the twi bus is a multi master bus, it is possible that two devices initiate a transaction at the same time. this results in multiple masters owni ng the bus simultaneously. this is solved using an arbitration scheme where the master lo ses control of the bus if it is not able to trans mit a high level on the sda line. the masters who lose arbitration must then wait until the bus becomes idle (i.e. wait for a stop condition) before attempting to reacquire bus ownership. slave devices are not involved in the arbitration procedure. sda scl s ack/nack bit 0 bit 7 bit 6 periodic clock stretching random clock stretching wakeup clock stretching
186 8077b?avr?06/08 xmega a figure 17-9. twi arbitration figure 17-9 shows an example where two twi masters are contending for bus ownership. both devices are able to issue a start condition, but device1 loses arbitration when attempting to transmit a high level (bit 5) while device2 is transmitting a low level. arbitration between a repeated start condition and a data bit, a stop condition and a data bit, or a repeated start conditi on and stop condition are not allowed and will require special handling by software. 17.3.9 synchronization a clock synchronization algorithm is necessary fo r solving situations where more than one mas- ter is trying to control the scl line at the same time. the algorithm is based on the same principles used for clock stretching previously described. figure 17-10 shows an example where two masters are competing for the control over the bus clock. the scl line is the wired-and result of the two ma sters clock outputs. figure 17-10. clock synchronization a high to low transition on the scl line will force the line low for all masters on the bus and they start timing their low clock period. the timing length of the low clock period can vary between the masters. when a master (device1 in this case) has completed its low period it releases the scl line. however, the scl line will not go high before all masters have released it. conse- quently the scl line will be held low by the de vice with the longest low period (device2). devices with shorter low periods must insert a wa it-state until the clock is released. all masters start their high period when the scl line is released by all devices and has become high. the device1_sda sda (wired-and) device2_sda scl s bit 7 bit 6 bit 5 bit 4 device1 loses arbitration device1_scl scl (wired-and) wait state device2_scl high period count low period count
187 8077b?avr?06/08 xmega a device which first completes it s high period (device1) forces the clock line low and the proce- dure are then repeated. the result of this is that the device with the shortest clock period determines the high period while the low period of the clock is determined by the longest clock period. 17.4 twi bus state logic the bus state logic continuously monitors the activity on the twi bus lines when the master is enabled. it continues to operate in all sleep modes, including power down. the bus state logic includes start and stop cond ition detectors, collisi on detection, inactive bus timeout detection, and bit counter. this is used to determine the bus state. software can get the current bus state by reading the bus state bits in the master status register. the bus state can be 'unknown', 'idle', 'busy' or 'owner' and is determined according to the state diagram shown in figure 17-11 . the value of the bus state bits according to state is shown in binary in the figure. figure 17-11. bus state, state diagram after a system reset, the bus state is unknown. from this the bus state machine can be forced to enter idle by writing to the bus state bits accordingly. if no state is set by application software the bus state will become idle w hen a stop condition is detect ed. if the master inactive bus timeout is enabled the bus state will change to idle on the occurrence of a timeout. after a known bus state is established th e bus state will not re-enter the unknown state from any of the other states. only a system rese t or disabling the twi master will set the state to unknown. when the bus is idle it is ready for a new tr ansaction. if a start condition generated externally is detected, the bus becomes bu sy until a stop condition is detected. the st op condition will change the bus state to idle. if the master inactive bus timeout is enabled bus state will change from busy to idle on the occurrence of a timeout. p + timeout write address idle (0b01) s busy (0b11) unknown (0b00) owner (0b10) arbitration lost command p write address(sr) sr (s) reset port timeout
188 8077b?avr?06/08 xmega a if a start condition is generated internally while in idle state the owner state is entered. if the complete transaction was performed without interference, i.e. no collisions are detected, the master will issue a stop conditi on and the bus stat e changes back to idle. if a collision is detected the arbitration is assumed lost and the bus state becomes busy until a stop condition is detected. a repeated start co ndition will only change the bus state if arbi tration is lost dur- ing the issuing of the repeated start. 17.5 twi master operation the twi master is byte-oriented with optional interrupt after each byte. there are separate inter- rupts for master write and master read. interrupt flags can also be used for polled operation. there are dedicated status flags for indicating ac k/nack received, bus error, arbitration lost, clock hold and bus state. when an interrupt flag is set, th e scl line is forced low. this will give the master time to respond or handle any data, and will in most cases requi re software interaction. figure 17-12 shows the twi master operation. the diamond shaped symbols (sw) indicate where software interaction is required. clearing the interrupt flags, releases the scl line. figure 17-12. twi master operation the number of interrupts generated is kept at a minimum by automatic handling of most condi- tions. quick command and smart mode can be enabled to auto trigger operations and reduce software complexity. idle s busy busy p sr p m3 m3 m2 m2 m1 m1 r data address w a/a data wait for idle application sw sw sr p m3 m2 busy m4 a sw a/a a/a a/a m4 a idle idle master read interrupt + hold master write interrupt + hold sw sw sw busy r/w sw driver software the master provides data on the bus slave provides data on the bus a a r/w busy m4 bus state mn diagram connections
189 8077b?avr?06/08 xmega a 17.5.1 transmitting address packets after issuing a start condition, the master starts performing a bus transaction when the mas- ter address register is written with the slave address and direction bit. if the bus is busy the twi master will wait until the bus becom es idle. when the bus is idle the master will issue a start condition on the bus before the address byte is transmitted. depending on arbitration and the r/w direction bit one of four distinct cases (1 to 4) arises fol- lowing the address packet. the different cases must be handled in software. 17.5.1.1 case m1: arbitration lost or bus error during address packet if arbitration is lost during the sending of the address packet the master write interrupt flag and arbitration lost flag are both set. serial data output to the sda line is disabled and the scl line is released. the master is no longer allowed to perform any operation on the bus until the bus state has changed back to idle. a bus error will behave in the same way as an arbitr ation lost condition, but the error flag is set in addition to write interrupt flag and arbitration lost flag. 17.5.1.2 case m2: address packet transmit complete - address not acknowledged by slave if no slave device responds to the address the master write interrupt flag is set and the master received acknowledge flag is set. the clock hold is active at this point preventing further activity on the bus. 17.5.1.3 case m3: address packet transmit complete - direction bit cleared if the master receives an ack from the slave, the master write interrupt flag is set, and the master received acknowledge flag is cleared. th e clock hold is active at this point preventing further activity on the bus. 17.5.1.4 case m4: address packet transmit complete - direction bit set if the master receives an ack from the slave, the master proceeds receiving the next byte of data from the slave. when the first data byte is received the master read interrupt flag is set and the master received acknowledge flag is cleare d. the clock hold is active at this point pre- venting further activity on the bus. 17.5.2 transmitting data packets assuming case 3 above, the master can start transmitting data by writing to the master data reg- ister. if the transfer was successful the slave will signal with ack. the master write interrupt flag is set, the master received acknowledge flag is cleared and the master can prepare new data to send. during data transf er the master is cont inuously monitoring the bus for collisions. the received acknowledge flag must be checked for each data packet transmitted before the next data packet can be transferred. the master is not allowed to continue transmitting data if the slave signals a nack. if a collision is detected and the master looses arbitration during transfe r, the arbitration lost flag is set. 17.5.3 receiving data packets assuming case 4 above the master has already received one byte from the slave. the master read interrupt flag is set, and the master must prepare to receive new data. the master must respond to each byte with ack or nack. indica ting a nack might not be successfully executed
190 8077b?avr?06/08 xmega a since arbitration can be lost during the transmiss ion. if a collision is detected the master looses arbitration and the arbitration lost flag is set. 17.6 twi slave operation the twi slave is byte-oriented with optional interr upts after each byte. there are separate slave data interrupt and address/stop interrupt. interrupt flags can also be used for polled operation. there are dedicated status flags for indicating ack/nack received, clock hold, collision, bus error and read/write direction. when an interrup t flag is set, the scl line is forced lo w. this will give the slave time to respond or handle any data, and will in most cases require software interaction. figure 17-13 . shows the twi slave operation. the diamond shapes symbols (sw) indicate where software interaction is required. figure 17-13. twi slave operation the number of interrupts generated is kept at a minimum by automatic handling of most condi- tions. quick command can be enabled to auto trigger operations and reduce software complexity. promiscuous mode can be enabled to allow the slave to respond to all received addresses. 17.6.1 receiving address packets when the twi slave is properly configured, it will wait for a start condition to be detected. when this happens, the successi ve address byte will be receiv ed and checked by the address match logic, and the slave will ack the correct address. if the received address is not a match, the slave will not acknowledge the address and wait for a new start condition. the slave address/stop interrupt flag is set when a start condition succeeded by a valid address packet is detected. a general call address will al so set the interrupt flag. a start condition immediately followed by a st op condition, is an illegal operation and the bus error flag is set. s s3 address s2 a s1 r w data a/a data p s2 sr s3 p s2 sr s3 slave address interrupt slave data interrupt a collision (smbus) sw sw sw sw a/a a/a sw release hold s1 a s1 sw interrupt on stop condition enabled s1 sw driver software the master provides data on the bus slave provides data on the bus sn diagram connections
191 8077b?avr?06/08 xmega a the r/w direction flag reflects the direction bit received with the address. this can be read by software to determine the type of operation currently in progress. depending on the r/w direction bit and bus condition one of four distinct cases (1 to 4) arises following the address packet. the different cases must be handled in software. 17.6.1.1 case 1: address packet accepted - direction bit set if the r/w direction flag is set, this indicates a master read operation. the scl line is forced low, stretching the bus clock. if ack is sent by the slave, the slave hardware will set the data interrupt flag indicating data is needed for transmit . if nack is sent by the slave, the slave will wait for a new condition and address match. 17.6.1.2 case 2: address packet accepted - direction bit cleared if the r/w direction flag is cleared this indicates a master write operation. the scl line is forced low, stretching the bus clock. if ack is sent by the slave, the slave will wait for data to be received. data, repeated start or stop can be received after this. if nack is indicated the slave will wait for a new start condition and address match. 17.6.1.3 case 3: collision if the slave is not able to send a high level or na ck, the collision flag is set and it will disable the data and acknowledge output from the slave logi c. the clock hold is released. a start or repeated star t condition will be accepted. 17.6.1.4 case 4: stop condition received. operation is the same as case 1 or 2 above with one exception. when the stop condition is received, the slave address/stop flag will be set indicating that a stop condition and not an address match occurred. 17.6.2 receiving data packets the slave will know when an address packet with r/w direction bit cleared has been success- fully received. after acknowledging this, the slave must be ready to receive data. when a data packet is received the data interrupt flag is set, and the slave must indicate ack or nack. after indicating a nack, the slave must expect a stop or repeated start condition. 17.6.3 transmitting data packets the slave will know when an address packet, with r/w direction bit set, has been successfully received. it can then start sending data by writing to the slave data register. when a data packet transmission is completed, the data interrupt flag is set. if the master indicates nack, the slave must stop transmitting data, and expect a stop or repeated start condition. 17.7 enabling external driver interface an external drivers interface can be enabled. wh en this is done the internal twi drivers with input filtering and slew rate control are bypas sed. the normal i/o pin function is used and the direction must be configured by the user softwa re. when this mode is enabled an external twi compliant tri-state driver is needed for connecting to a twi bus. by default port pin 0 (pn0) and 1 (pn1) is used for sda and scl. the external driver interface uses port pin 0 to 3 for the signal s sda_in, scl_in, sda_out and scl_out.
192 8077b?avr?06/08 xmega a 17.8 register descrip tion - twi control 17.8.1 ctrl? twi common control register ? bit 7:2 - res: reserved these bits are unus ed and reserved for future use. for compatibility with futu re devices, always write these bits to zero when this register is written. ? bit 1 - sdahold: sda hold time enable. setting this bit to one enables an internal hold time on sda with respect to the negative edge of scl. ? bit 0 - edien: external driver interface enable setting this bit enables the use of the external driver interface, clearing this bit enables normal two wire mode. see table 17-1 for details. 17.9 register descrip tion - twi master 17.9.1 ctrla - twi master control register a ? bit 7:6 - intlvl[1:0]: interrupt level the interrupt level (intlvl) bit select the interrupt level for the twi master interrupts. ? bit 5 - rien: read interrupt enable setting the read interrupt enable (rien) bit enables the read interrupt when the read interrupt flag (rif) in the status register is set. in addition the intlvl bits must be unequal zero for twi master interrupts to be generated. bit 76543210 +0x00 ------sdaholdedienctrl read/writerrrrrrr/wr/w initial value00000000 table 17-1. external driver interface enable edien mode comment 0normal twi two pin interface, slew rate control and input filter. 1 external driver interface four pin interface, standard i/o, no slew-rate control, no input filter. bit 76543210 +0x01 intlvl[1:0] rien wien enable - - - ctrla read/write r/w r/w r/w r/w r/w r r r initial value00000000
193 8077b?avr?06/08 xmega a ? bit 4 - wien: write interrupt enable setting the write interrupt enable (wien) bit enables the write interrupt when the write interrupt flag (wif) in the status register is set. in addition the intlvl bits must be unequal zero for twi master interrupts to be generated. ? bit 3 - enable: enable twi master setting the enable twi master (enable) bit enables the twi master. ? bit 2:0 - res: reserved these bits are unus ed and reserved for future use. for compatibility with futu re devices, always write these bits to zero when this register is written. 17.9.2 ctrlb - twi master control register b ? bit 7:4 - res: reserved bits these bits are unus ed and reserved for future use. for compatibility with futu re devices, always write these bits to zero when this register is written. ? bit 3:2 - timeout[1:0]: inactive bus timeout setting the inactive bus ti meout (timeout) bits un equal zero will enable the inactive bus time- out supervisor. if the bus is inactive for longer than the timeout settings, the bus state logic will enter the idle state. figure 17-2 lists the timeout settings. ? bit 1 - qcen: quick command enable setting the quick command enable (qcen) bit enables quick command. when quick com- mand is enabled, a stop condition is sent immediate after the slave acknowledges the address. ? bit 0 - smen: smart mode enable setting the smart mode enable (smen) bit enables smart mode. when smart mode is enabled, the acknowledge action, as set by the ackact bit in control register c, is sent immediately after reading the data register. bit 76543210 +0x02 - - - - timeout[1:0] qcen smen ctrlb read/write r r r r r/w r/w r/w r/w initial value00000000 table 17-2. twi master inactive bus timeout settings timeout[1:0] group configuration description 00 disabled disabled, normally used for i 2 c 01 50us 50 s, normally used for smbus at 100 khz 10 100us 100 s 11 200us 200 s
194 8077b?avr?06/08 xmega a 17.9.3 ctrlc - twi master control register c ? bits 7:3 - res: reserved these bits are unus ed and reserved for future use. for compatibility with futu re devices, always write these bits to zero when this register is written. ? bit 2 - ackact: acknowledge action the acknowledge action (ackact) bit defines the master's acknowledge behavior in master read mode. the acknowledge action is executed when a command is written to the cmd bits. if smen in control register b is set, the acknowledge action is performed when the data regis- ter is read. table 17-3 lists the acknowledge actions. ? bit 1:0 - cmd[1:0]: command writing the command (cmd) bits triggers a master operation as defined by table 17-4 . the cmd bits are strobe bits, and always read as zero. the acknowledge action is only valid in mas- ter read mode (r). in master write mode (w ), a command will only re sult in a repeated start or stop condition. the ackact bit and the cmd bits can be written at the same time, and then the acknowledge action will be updated before the command is triggered. writing a command to the cmd bits will clear t he master interrupt flag s and the clkhold flag. bit 76543210 +0x03 - - - - - ackact cmd[1:0] ctrlc read/writerrrrrr/wr/wr/w initial value00000000 table 17-3. ackact bit description ackact action 0 send ack 1 send nack table 17-4. cmd bit description cmd[1:0] mode operation 00 x reserved 01 x execute acknowledge action succeeded by repeated start condition 10 w no operation r execute acknowledge action succeeded by a byte receive 11 x execute acknowledge action succeeded by issuing a stop condition
195 8077b?avr?06/08 xmega a 17.9.4 status - master status register ? bit 7 - rif: read interrupt flag this read interrupt flag (rif) is set when a byte is successfully received in master read mode, i.e. no arbitration lost or bus error occurred during the operation. writing a one to this bit location will clear the rif. when this flag is set the master forces the scl line low, stretching the twi clock period. clearing the interr upt flags will release the scl line. this flag is also automatically cleared when: ? writing to the addr register. ? writing to the data register. ? reading the data register. ? writing a valid command to the cmd bits in the ctrlc register. ? bit 6 - wif: write interrupt flag the write interrupt flag (wif) flag is set when a byte is transmitted in master write mode. the flag is set regardless of the occurrence of a bus error or an arbitration lost condition. the wif is also set if arbitration is lost during sending of nack in master read mode, and if issuing a start condition when the bus state is unknown. writing a one to this bit location will clear the wif. when this flag is set the master forces the scl line low, stretching the twi clock period. clearing the interrupt flag s will release the scl line. the flag is also automatically cleared for the same conditions as rif. ? bit 5 - clkhold: clock hold the master clock hold (clkhold) flag is set wh en the master is holdi ng the scl line low. this is a status flag, and a read only bit that is set when the rif and wif is set. clearing the interrupt flags and releasin g the scl line, will indirectly clear this flag. the flag is also automatically cleared for the same conditions as rif. ? bit 4 - rxack: received acknowledge the received acknowledge (rxack) flag contains the most recently received acknowledge bit from slave. this is a read only flag. when read as zero the most recent acknowledge bit from the slave was ack, and when read as one the most recent acknowledge bit was nack. ? bit 3 - arblost: arbitration lost the arbitration lost (arblost) flag is set if arbi tration is lost while transmitting a high data bit, a nack bit, or while issuing a start or repeated start condition on the bus. writing a one to this bit location w ill clear the arblost flag. writing the addr register will auto matically clear the arblost flag. bit 76543210 +0x04 rif wif clkhold rxack arblost buserr busstate[1:0] status read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000
196 8077b?avr?06/08 xmega a ? bit 2 - buserr: bus error the bus error (buserr) flag is set if an illegal bus condition has occurred. an illegal bus condi- tion occurs if a repeated start or stop condition is detected, and the number of bits from the previous start condition is not a multiple of nine. writing a one to this bit location will clear the buserr flag. writing the addr register will auto matically clear the buserr flag. ? bit 1:0 - busstate[1:0]: bus state the bus state (busstate) bits indicate the current twi bus state as defined in table 17-5 . the change of bus state is dependent on bus activity. refer to the section 17.4 ?t wi bus state logic? on page 187 . writing 01 to the busstate bits forces the bus state logic into idle state. the bus state logic cannot be forced into any other state. when the master is disabled, and after reset the bus state logic is disabled and the bus state is unknown. 17.9.5 baud - twi baud rate register the baud rate (baud) register defines the relation between the system clock and the twi bus clock (scl) frequency. the frequency relation can be expressed by using the following equation: [1] the baud register must be set to a value that results in a twi bus clock frequency (ftwi) equal or less 100 khz or 400 khz dependent on standard used by the application. the following equa- tion [2] expresses equation [1] with respect to the baud value: [2] the baud register should be written while the master is disabled. table 17-5. twi master bus state busstate[1:0] group configuration description 00 unknown unknown bus state 01 idle idle 10 owner owner 11 busy busy bit 76543210 +0x05 baud[7:0] baud read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 f twi f sys 2(5 twmbr ) + --------------------------------------- - [hz] = twmbr f sys 2 f twi ------------- - 5 ? =
197 8077b?avr?06/08 xmega a 17.9.6 addr - twi master address register when the address (addr) register is written with a slave address and the r/w -bit while the bus is idle, a start condition is issued, and the 7-bit slave address and the r/w -bit are transmitted on the bus. if the bus is already owned when addr is written, a repeated start is issued. if the previous transaction was a master read and no acknowledge is sent yet, the acknowledge action is sent before the repeated start condition. after completing the operation and the acknowledge bit from the slave is received, the scl line is forced low if arbitration was not lost. the wif is set. if the bus state is unknown when addr is written. the wif is set, and the buserr flag is set. all twi master flags are automatically cleared when addr is written. this includes buserr, arblost, rif, and wif. the master addr can be read at any time without interfering with ongoing bus activity. 17.9.7 data -twi master data register the data (data) register is used when transmitting and receiving data. during data transfer, data is shifted from/to the data register and to/from the bus. this implies that the data register cannot be accessed during byte transfers, and this is protected in hardware. the data register can only be accessed when the scl line is held low by the master, i.e. when clkhold is set. in master write mode, writing th e data register will trigger a data byte transfer, followed by the master receiving the acknowledge bit from the slave. the wif and the clkhold flag are set. in master read mode the rif and the clkhold flag are set when one byte is received in the data register. if smart mode is enabled, reading th e data register will trigger the bus opera- tion as set by the ackact bit. if a bus error occurs during reception the wif and buserr flag are set instead of the rif. accessing the data register will clear the master interrupt flags an d the clkhold flag. bit 76543210 +0x06 addr[7:0] addr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 +0x07 data[7:0] data read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000
198 8077b?avr?06/08 xmega a 17.10 register descr iption - twi slave 17.10.1 ctrla - twi slav e control register a ? bit 7:6 - intlvl[1:0]: twi slave interrupt level the slave interrupt level (intlvl) bits select the interrupt level for the twi slave interrupts. ? bit 5 - dien: data interrupt enable setting the data interrupt enable (dien) bit enables the data interrupt when the data interrupt flag (dif) in the status register is set. the intlvl bits must be unequal zero for the interrupt to be generated. ? bit 4 - apien: address/stop interrupt enable setting the address/stop interrupt enable (apien) bit enables the address/stop interrupt when the address/stop interrupt flag (apif) in the stat us register is set. the intlvl bits must be unequal zero for interrupt to be generated. ? bit 3 - enable: enable twi slave setting the enable twi slave (enable) bit enables the twi slave. ? bit 2 - pien: stop interrupt enable setting the stop interrupt enable (pien) bit will set the apif in the status register when a stop condition is detected. ? bit 1 - pmen: promiscuous mode enable by setting the promiscuous mode enable (pmen) bit, the slave address match logic responds to all received addresses. if this bit is cleared, the address match logic uses the addr register to determine which address to recognize as its own address. ? bit 0 - smen: smart mode enable setting the smart mode enable (smen) bit enables smart mode. when smart mode is enabled, the acknowledge action, as set by the ackact bit in the ctrlb register, is sent immediately after reading the data register. 17.10.2 ctrlb - twi slav e control register b bit 765432 1 0 +0x00 intlvl[1:0] dien apien enable pien pmen smen ctrla read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value000000 0 0 bit 76543210 +0x01 -----ackactcmd[1:0]ctrlb read/write r r r r r r/w r/w r/w initial value00000000
199 8077b?avr?06/08 xmega a ? bit 7:3 - res: reserved these bits are unus ed and reserved for future use. for compatibility with futu re devices, always write these bits to zero when this register is written. ? bit 2 - ackact: acknowledge action the acknowledge action (ackact) bit defines the slave's acknowledge behavior after an address or data byte is received from the ma ster. the acknowledge action is executed when a command is written to the cmd bits. if the smen bit in the ctrla register is set, the acknowl- edge action is performed when the data register is read. table 17-6 lists the acknowledge actions. ? bit 1:0 - cmd[1:0]: command writing the command (cmd) bits triggers the slave operation as defined by table 17-7 . the cmd bits are strobe bits, and always read as zero. the operation is dependent on the slave interrupt flags, dif and apif. the acknowledge ac tion is only executed when the slave receives data bytes or address byte from the master. writing the cmd bits will automatically clear th e slave interrupt flags , the clkhold flag and release the scl line. the ackact bit and cmd bits can be written at the same time, and then the acknowledge action will be updated before the command is triggered. table 17-6. twi slave acknowledge action ackact action 0 send ack 1 send nack table 17-7. twi slave command cmd[1:0] dir operation 00 x no action 01 x reserved 10 used to complete transaction 0 execute acknowledge action succeeded by waiting for any start (s/sr) condition. 1 wait for any start (s/sr) condition. 11 used in response to an address byte (apif is set) 0 execute acknowledge action succeeded by reception of next byte. 1 execute acknowledge action succeeded by the dif being set used in response to a data byte (dif is set ) 0 execute acknowledge action succeeded by waiting for the next byte. 1 no operation.
200 8077b?avr?06/08 xmega a 17.10.3 status? twi slave status register ? bit 7 - dif: data interrupt flag the data interrupt flag (dif) is set when a data by te is successfully received, i.e. no bus error or collision occurred during the operation. writi ng a one to this bit location will clear the dif. when this flag is set the slave forces the scl line low, stretching the twi clock period. clearing the interrupt flags w ill release the scl line. this flag is also automatically cleared when: 1. writing to the slave data register 2. reading the slave data register 3. writing a valid command to the cmd bits in the ctrlb register ? bit 6 - apif: address/stop interrupt flag the address/stop interrupt flag (apif) is set when the slave detects that a valid address has been received, or when a transmit collision is detect ed. if the pien bit in the ctrla register is set a stop condition on the bus will also set apif. writing a one to this bi t location will clear the apif. when this flag is set the slave forces t he scl line low, stretching the twi clock period. clearing the interrupt flag s will release the scl line. the flag is also automatically cleared for the same conditions as dif. ? bit 5 - clkhold: clock hold the slave clock hold (clkhold) flag is set when the slave is holding the scl line low.this is a status flag, and a read only bit that is set when the dif or apif is set. clearing the interrupt flags and releasing the scl line, will indirectly clear this flag. ? bit 4 - rxack: received acknowledge the received acknowledge (rxack) flag contains the most recently received acknowledge bit from the master. this is a read only flag. wh en read as zero the most recent acknowledge bit from the maser was ack, and when read as one the most recent acknowledge bit was nack. ? bit 3 - coll: collision the slave collision (coll) flag is set when slave is not been able to transfe r a high data bit or a nack bit. if a collision is detected, the slav e will commence its normal operation, disable data and acknowledge output, and no low values will be shifted out onto the sda line. writing a one to this bit location will clear the coll flag. the flag is also automatically cleared when a start or repeated start condition is detected. ? bit 2 - buserr: twi slave bus error the slave buss error (buserr) flag is set w hen an illegal bus condition has occurs during a transfer. an illegal bus condition occurs if a repeated start or stop condition is detected, bit 76543210 +0x02 dif apif clkhold rxack coll buserr dir ap status read/write r/w r/w r/w r r/w r/w r/w r/w initial value00000000
201 8077b?avr?06/08 xmega a and the number of bits from the previous start condition is not a multiple of nine. writing a one to this bit location will clear the buserr flag. for bus errors to be detected, the bus state logic must be enabled. this is done by enable twi master. ? bit 1 - dir: read/write direction the read/write direction (dir) flag reflects t he direction bit from the last address packet received from a master. when this bit is read as one, a master read operation is in progress. when read as zero a master write operation is in progress. ? bit 0 - ap: slave address or stop the slave address or stop (ap) flag indicates whether a valid address or a stop condition caused the last setting of the apif in the status register. 17.10.4 addr - twi slave address register the slave address (addr) regist er contains the twi slave address used by the slave address match logic to determine if a master has addressed the slave. when using 7-bit or 10-bit address recognition mode, the up per 7-bits of the address regist er (addr[7:1]) represents the slave address. the least significant bit (addr[0]) is used for general call address recognition. setting addr[0] enables general call address recognition logic. when using 10-bit addressing the address match logic only support hardware address recogni- tion of the first byte of a 10-bit address. by setting addr[7:1] = "0b11110nn", 'nn' represents bit 9 and 8 or the slave address. the next byte receiv ed is bit 7 to 0 in the 10-bit address, and this must be handled by software. when the address match logic detects that a valid address byte is received, the apif is set, and the dir flag is updated. if the pmen bit in the ctrla register is set, the address match logic responds to all addresses transmitted on the twi bus. the addr register is not used in this mode. table 17-8. twi slave address or stop ap description 0 a stop condition generated the interrupt on apif 1 address detection generated the interrupt on apif bit 76543210 +0x03 addr[7:0] addr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0
202 8077b?avr?06/08 xmega a 17.10.5 data - twi slave data register the data (data) register is used when transm itting and received data. during data transfer, data is shifted from/to the data register and to/from the bus. this implies that the data register cannot be accessed during byte transfers, and this is protected in hardware. the data register can only be accessed when the scl line is held low by the slave, i.e. when clkhold is set. when a master is reading data from the slave, data to send must be written to the data regis- ter. the byte transfer is started when the mast er start to clock the data byte from the slave, followed by the slave receiving the acknowledge bit from the master. the dif and the clkhold flag are set. when a master write data to the slave the dif and the clkhold flag are set when one byte is received in the data register. if smart mode is enabled, reading the data register will trigger the bus operation as set by the ackact bit. accessing the data register will clear the slave interrupt flags and the clkhold flag. bit 76543210 +0x04 data[7:0] data read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000
203 8077b?avr?06/08 xmega a 17.11 register summary - twi 17.12 register summary - twi master 17.13 register summary - twi slave address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page +0x00 ctrl - - - - - - sdahold edien 192 +0x01 master offset address for twi master +0x08 slave offset address for twi slave address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page +0x01 ctrla intlvl[1:0] rien wien enable - - - 192 +0x02 ctrlb - - - - timeout[1:0] qcen smen 193 +0x03 ctrlc - - - - - ackact cmd[1:0] 194 +0x04 status rif wif clkhold rxack arblost buserr busstate[1:0] 195 +0x05 baud baud[7:0] 196 +0x06 addr addr[7:0] 197 +0x07 data data[7:0] 197 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page +0x00 ctrla intlvl[1:0] dien apien enable pien tpmen smen 198 +0x01 ctrlb - - - - - ackact cmd[1:0] 198 +0x02 status dif apif clkhold rxack coll buserr dir ap 200 +0x03 addr addr[7:0] 201 +0x04 data data[7:0] 202
204 8077b?avr?06/08 xmega a 18. spi ? serial peripheral interface 18.1 features ? full-duplex, three-wire synchronous data transfer ? master or slave operation ? lsb first or msb first data transfer ? eight programmable bit rates ? end of transmission interrupt flag ? write collision flag protection ? wake-up from idle mode ? double speed (ck/2) master spi mode 18.2 overview the serial peripheral interfac e (spi) is a high-speed synchronous data transfer interface using three or four pins. it allows fast communication between an xmega device and peripheral devices or between several avr devices. th e spi supports full duplex communication. a device connected to the bus must act as a master or slave.the master initiates and controls all data transactions. the interconnection between master and slave cpus with spi is shown in figure 18-1 on page 204 . the system consists of two shift registers, and a master clock gener- ator. the spi master initiates the communicati on cycle when pulling low the slave select (ss ) pin of the desired slave. master and slave prepare the data to be sent in their respective shift registers, and the master generates the required clock pulses on the sck line to interchange data. data is always shifted from master to slave on the master out - slave in (mosi) line, and from slave to master on the master in - slave out (miso) line. after each data packet, the mas- ter can synchronize the slave by pulling high the ss line. figure 18-1. spi master-slave interconnection the xmega spi module is single buffered in the transmit direction and double buffered in the receive direction. this means that bytes to be transmitted cannot be written to the spi data reg- ister before the entire shift cycle is completed. when receiving data, a received character must be read from the data register before the next character has been completely shifted in. other- wise, the first byte is lost. shift enable
205 8077b?avr?06/08 xmega a in spi slave mode, the control logic will sample the incoming signal of the sck pin. to ensure correct sampling of this clock signal, the minimum low and high periods must be: low period: longer than 2 cpu clock cycles. high period: longer than 2 cpu clock cycles. when the spi module is enabled, the data direction of the mosi, miso, sck, and ss pins is overridden according to table 18-1 . the pins with user defined direction, must be configured from software to have the correct direction according to the application. 18.3 master mode when configured as a master, the spi interface has no automatic control of the ss line. the ss pin must be configured as output, and controlled by user software. if the bus consists of several spi slaves and/or masters, a spi master can use general i/o pins to control the ss line to each of the slaves on the bus. writing a byte to the data register starts the spi clock generator, and the hardware shifts the eight bits into the selected slave. after shifting one byte, the spi clock generator stops and the spi interrupt flag is set. the master may continue to shift the next byte by writing new data to the data register, or signal the end of transfer by pulling the ss line high. the last incoming byte will be kept in the buffer register. if the ss pin is configured as an input, it must be held high to ensure master operation. if the ss pin is input and being driven low by external circuitry, the spi module will interpret this as another master trying to take control of the bus. to avoid bu s contention, the ma ster will take the following action: 1. the master enters slave mode. 2. the spi interrupt flag is set. 18.4 slave mode when configured as a slave, the spi interface will remain sleeping with miso tri-stated as long as the ss pin is driven high. in this state, software may update the contents of the data register, but the data will not be shifte d out by incoming clock pulses on the sck pin until the ss pin is driven low. if ss is driven low and assuming the miso pin is configur ed as output, the slave will start to shift out data on the first sck clock pulse. as one byte has been completely shifted, the spi interrupt flag is set. the slave may continue to place new data to be sent into the data reg- ister before reading the incoming data. the last incoming byte will be kept in the buffer register. when ss is driven high, the spi logic is reset, an d the spi slave will not receive any data. any partially received packet in the shift register will be dropped. table 18-1. spi pin overrides pin direction, master spi direction, slave spi mosi user defined input miso input user defined sck user defined input ss user defined input
206 8077b?avr?06/08 xmega a as the ss pin is used to signal start and end of trans fer, it is also usef ul for doing packet/byte synchronization, keeping the slave bit counter synchronous with the master clock generator. 18.5 data modes there are four combinations of sck phase and polarity with respect to serial data. the spi data transfer formats are shown in figure 18-2 . data bits are shifted out and latched in on opposite edges of the sck signal, ensuring suffici ent time for data signals to stabilize. leading edge is the first clock edge in a clock cycl e. trailing edge is the last clock edge in a clock cycle. figure 18-2. spi transfer modes table 18-2. spi modes mode leading edge trailing edge 0 rising, sample falling, setup 1 rising, setup falling, sample 2 falling,sample rising, setup 3 falling, setup rising, sample bit 1 bit 6 l s b m s b mode 0 s ample i mo s i/mi s o change 0 mo s i pin change 0 mi s o pin mode 2 ss m s b l s b bit 6 bit 1 bit 5 bit 2 bit 4 bit 3 bit 3 bit 4 bit 2 bit 5 m s b first (dord = 0) l s b first (dord = 1) mode 1 s ample i mo s i/mi s o change 0 mo s i pin change 0 mi s o pin mode 3 ss m s b l s b bit 6 bit 1 bit 5 bit 2 bit 4 bit 3 bit 3 bit 4 bit 2 bit 5 bit 1 bit 6 l s b m s b m s b first (dord = 0) l s b first (dord = 1)
207 8077b?avr?06/08 xmega a 18.6 dma support dma support on the spi module is only available in slave mode. the spi slave can trigger a dma transfer as one byte has been shifted into the data register. it is possible to set up the xmega usart in spi mode to have dma suppo rt for master mode, for details refer to section 19.10 ?usart in master spi mode? on page 222 . 18.7 register description 18.7.1 ctrl - spi control register ? bit 7 - clk2x: spi clock double when this bit is set the spi speed (sck freq uency) will be doubled in master mode (see table 18-4 on page 208 ). ? bit 6 - enable: spi enable setting this bit enables the spi modules. this bit must be set to enable any spi operations. ? bit 5 - dord: data order dord decide the data order when a byte is shifted out from the data register. when dord is written to one, the lsb of the data byte is transmitted first, and when dord is written to zero, the msb of the data byte is transmitted first. ? bit 4 - master: master/slave select this bit selects master mode when written to one, and slave mode when written to zero. if ss is configured as an input and is driven low while master is set, master will be cleared. ? bit 3:2 - mode[1:0]: spi mode these bits select the transfer mode. the four combinations of sck phase and polarity with respect to serial data is shown in figure 18-3 on page 207 . this decide whether the first edge in a clock cycles (leading edge) is ri sing or falling, and if data setup and sample is on lading or trail- ing edge. when the leading edge is rising the bit sck is low when idle, and when the leading edge is fall- ing the sck is high when idle. table 18-3. spi transfer modes bit 76543210 +0x00 clk2x enable dord master mode[1:0] prescaler[1:0] ctrl read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 mode[1:0] group configuration leading edge trailing edge 00 0 rising, sample falling, setup 01 1 rising, setup falling, sample 10 2 falling,sample rising, setup 11 3 falling, setup rising, sample
208 8077b?avr?06/08 xmega a ? bits 1:0 - prescaler[1:0 ]: spi clock prescaler these two bits control the sck rate of the device configured in a master mode. these bits have no effect in slave mode. the relationship between sck and the peripheral clock frequency (clk- per )is shown in table 18-4 on page 208 . 18.7.2 intctrl - spi interrupt control register ? bits 7:2 - res: reserved these bits are unus ed and reserved for future use. for compatibility with futu re devices, always write these bits to zero when this register is written. ? bits 1:0 - intlvl[1:0]: spi interrupt level these bits enable the spi interrupt and select the interrupt level as described in section 11. ?interrupts and programmable multi-level interrupt controller? on page 108 . the enabled inter- rupt will be triggered when the if in the st atus register is set. 18.7.3 status - spi status register ? bit 7 - if: spi interrupt flag when a serial transfer is complete and one byte is completely shifted in/out of the data regis- ter, the if bit is set. if ss is an input and is driven low when the spi is in ma ster mode, this will also set the if bit. the if is cleared by hardware when executing the corresponding interrupt handling vector. alternatively, the spif bit can be cleared by first reading the status register with if set, and then access the data register. table 18-4. relationship between sck and the peripheral clock (clk per ) frequency clk2x prescaler[1:0] sck frequency 000clk per /4 001clk per /16 010clk per /64 011clk per /128 100clk per /2 101clk per /8 110clk per /32 111clk per /64 bit 76543210 +0x01 ------ intlvl[1:0]intctrl read/writerrrrrrr/wr/w initial value00000000 bit 76543210 +0x02 spifwcol------status read/writerrrrrrrr/w initial value 0 0 0 0 0 0 0 0
209 8077b?avr?06/08 xmega a ? bit 6 - wrcol: write collision flag the wrcol bit is set if the data register is written during a data transfer. the wrcol bit is cleared by first reading the status register with wrcol set, and then accessing the data register. ? bit 5:0 - res: reserved these bits are reserved and will always be read as zero. for compatibility with future devices, always write these bits to zero when this register is written. 18.7.4 data - spi data register the data register used for sending and receiving data. writing to the register initiates the data transmission, and the byte written to the register will be shifted out on th e spi output line. read- ing the register causes the shift register receive buffer to be read, and return the last bytes successfully received. 18.8 register summary bit 76543210 +0x03 data[7:0] data read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page +0x00 ctrl clk2x enable dord master mode[1:0] prescaler[1:0] 207 +0x01 intctrl - - - - - - intlvl[1:0] 208 +0x02 status if wrcol - - - - - - 208 +0x03 data data[7:0] 209
210 8077b?avr?06/08 xmega a 19. usart 19.1 features ? full duplex operation (independent se rial receive and transmit registers) ? asynchronous or synchronous operation ? master or slave clocked synchronous operation ? enhanced baud rate generator ? supports serial frames with 5, 6, 7, 8, or 9 data bits and 1 or 2 stop bits ? odd or even parity generation and parity check supported by hardware ? data overrun and framing error detection ? noise filtering includes false start bit detection and digital low pass filter ? separate interrupts on tx complete, tx data register empty and rx complete ? multi-processor communication mode ? double speed asynchronous communication mode ? master spi mode, three-wire synchronous data transfer ? supports all four spi modes of operation (mode 0, 1, 2, and 3) ? lsb first or msb first data tr ansfer (configurable data order) ? queued operation (double buffered) ? high speed operation (f xck,max = f per /2) ? ircom module for irda compliant pulse modulation/demodulation 19.2 overview the universal synchronous and asynchronous serial receiver and transmitter (usart) is a highly flexible serial communica tion module. the usart supports full duplex communication, and both asynchronous and clocked synchronous operation. the usart can be set in master spi compliant mode and be used for spi communication. communication is frame based, and the frame format can be customized to support a wide range of standards. the usart is buffered in both direction, enabling continued data transmis- sion without any delay between frames. there are separate interrupt vectors for receive and transmit complete, enabling fully interrupt driven communication. frame error and buffer over- flow are detected in hardware and indicated with separate status flags. even or odd parity generation and parity check can also be enabled. a block diagram of the usart is shown in figure 19-1 on page 211 . the main parts are the clock generator, the transmitter and the receiver, indicated in dashed boxes.
211 8077b?avr?06/08 xmega a figure 19-1. usart block diagram the clock generation logic has a fractional baud rate generator that is able to generate a wide range of usart baud rates. it also includes sync hronization logic for exte rnal clock input in syn- chronous slave operation. the transmitter consists of a single write buffe r (data), a shift register, parity generator and control logic for handling different frame formats. the write buffer allows continuous data trans- mission without any delay between frames. the receiver consists of a two level fifo receive buffer (data), and a shift register. data and clock recovery units ensure robust synchronization and noise filtering during asynchronous data reception. it includes frame error, buffer overflow and parity error detection. when the usart is set in master spi compliant mode, all usart specif ic logic is disabled, leaving the transmit and receive buffers, shift registers, and baud rate generator enabled. pin control and interrupt generation is identical in both modes. the registers are used in both modes, but the functionality differs for some control settings. an ircom module can be enabled for one usart to support irda 1.4 physical compliant pulse modulation and demodulation for baud rates up to 115.2 kbps. refer to section 20. ?ircom - ir communication module? on page 231 for details. parity generator bsel [h:l] data (transmit) ctrla ctrlb ctrlc baud rate generator fractional devide transmit shift register receive shift register rxd txd pin control data (receive) pin control xck data recovery clock recovery pin control tx control rx control parity checker data bus osc sync logic clock generator transmitter receiver
212 8077b?avr?06/08 xmega a 19.3 clock generation the clock used for baud rate generation, and for shifting and sampling data bits is generated internally by the fractional baud rate generator or externally from the transfer clock (xck) pin. five modes of clock generation are supported: normal and double speed asynchronous mode, master and slave synchronous mode, and master spi mode. figure 19-2. clock generation logic, block diagram.i 19.3.1 internal clock generation - the fractional baud rate generator the fractional baud rate generator is used for internal clock generation for asynchronous modes, synchronous master mode, and spi master mode operation. the generated output fre- quency (f baud ) is given by the period setting (bsel), an optional scale setting (bsacle) and the peripheral clock frequency (f per ). table 19-1 on page 213 contains equations for calculating the baud rate (in bits per second) and for calculati ng the bsel value for each mode of operation. bsel can be set to any va lue between 0 and 4095. fractional baud rate generation can be used in asynchronous mode of operation to increase the average resolution. a scale factor (bscale) allows the baud rate to be optionally left or right scaled. choosing a positive scale value will result s in right scaling, which increase the period and consequently reduce the frequency of the produced baud rate, without changing the resolu- tion. if the scale value is negative the divider uses fractional arithmetic counting to increase the resolution by distributing the fractional divide va lue over time. bscale can be set to any value from -7 to +7, wher e 0 implies no scaling. baud rate generator /2 bsel /4 /2 sync register f osc xck pin txclk u2x umsel [1] ddr_xck 0 1 0 1 xcki xcko ddr_xck rxclk 0 1 1 0 edge detector port_inv f baud
213 8077b?avr?06/08 xmega a note: 1. the baud rate is defined to be the transfer rate in bit per second (bps) 19.3.2 external clock external clock is used in synchronous slave mode operation. the xck clock input is sampled on the peripheral clock frequency (f per ) by a synchronization register to minimize the chance of meta-stability. the output from the synchronization register is then pass ed through an edge detector. this process introduces a delay of two peripheral clock periods, and therefore the max- imum external xck clock frequency (f xck )is limited by the following equation: each high and low period the xck clock cycles must be sampled twice by the peripheral clock. if the xck clock has jitter, or the high/low pe riod duty cycle is not 50/50, the maximum xck clock speed must be reduced accordingly. 19.3.3 double speed operation (clk2x) double speed operation can be enabled to allow for higher baud rates on lower peripheral clock frequencies under asynchronous operation. when double speed operation is enabled the baud rate for a given asynchronous baud rate setting as shown in table 19-1 on page 213 will be dou- bled. in this mode the receiver will use half the number of samples (reduced from 16 to 8) for data sampling and clock recovery. due to the reduced sampling more accurate baud rate setting and peripheral clock are required. see section 19.8 ?asynchronous data reception? on page 218 for more details on accuracy. table 19-1. equations for calculating baud rate register setting operating mode conditions equation for calculation baud rate (1) equation for calculation bsel value asynchronous normal speed mode (clk2x = 0) bscale 0 bscale < 0 asynchronous double speed mode (clk2x = 1) bscale 0 bscale < 0 synchronous and spi master mode f baud f per 2 bscale 16 bsel ?? () 1 + ------------------------------------------------------------------ = bsel f per 2 bscale 16 ? f baud ------------------------------------------------ 1 ? = f baud f per 16((2 bscale bsel ) ? 1) + ------------------------------------------------------------------ - = bsel 1 2 bscale --------------------- f per 16 f baud --------------------- - 1 ? ?? ?? = f baud f per 2 bscale 8 bsel ?? () 1 + --------------------------------------------------------------- = bsel f per 2 bscale 8 ? f baud --------------------------------------------- 1 ? = f baud f per 8((2 bscale bsel ) ? 1) + --------------------------------------------------------------- - = bsel 1 2 bscale --------------------- f per 8 f baud ------------------ - 1 ? ?? ?? = f baud f per 2 bsel 1 + () ? ------------------------------------ - = bsel f per 2 f baud ------------------ - 1 ? = f xck f per 4 ---------- - <
214 8077b?avr?06/08 xmega a 19.3.4 synchronous clock operation when synchronous mode is used, the xck pin cont rols whether the transmission clock is input (slave mode) or output (master mode). the corresponding port pin must be set to output for master mode and to input for slave mode . the normal port operation of the xck pin will be over- ridden. the dependency between the clock edges and data sampling or data change is the same. data input (on rxd) is sampled at the opposite xck clock edge of the edge where data output (txd) is changed. figure 19-3. synchronous mode xckn timing. using the inverted i/o (inven) setting in the pi n configuration register for the corresponding xck port pin, it is selectable which xck clock edge is used for data sampling and which is used for data change. if inverted i/o is disabled (inven=0) data will be changed at rising xck clock edge and sampled at falling xck clock edge. if inverted i/o is enable d (inven=1) data will be changed at falling xck clock edge and sampled at rising xck cloc k edge. for more details, see in ?i/o ports? on page 106. 19.3.5 spi clock generation for spi operation only master mode with internal clock generation is supported. this is identical to the usart synchr onous master mode and th e baud rate or bsel se tting are calculated by using the same equations, see table 19-1 on page 213 . there are four combinations of the xck (sck) clock phase and polarity with respect to serial data, and these are determined by the clock phase (ucpha) control bit and the inverted i/o pin (inven) setting. the data transfer timing diagrams are shown in figure 19-4 on page 215 . data bits are shifted out and latched in on opposite edges of the xck signal, ensuring sufficient time for data signals to stabilize. the ucph a and inven settings are summarized in table 19-2 on page 214 . changing the setting of any of these bits during transmission will corrupt for both the receiver and transmitter. rxd / txd xck rxd / txd xck inven = 0 inven = 1 sample sample table 19-2. inven and ucpha functionality spi mode inven ucpha leading edge trailing edge 0 0 0 rising, sample falling, setup 1 0 1 rising, setup falling, sample 2 1 0 falling, sample rising, setup 3 1 1 falling, setup rising, sample
215 8077b?avr?06/08 xmega a leading edge is the first clock edge in a clock cycl e. trailing edge is the last clock edge in a clock cycle. figure 19-4. ucpha and inven data transfer timing diagrams. 19.4 frame formats data transfer is frame based, where a serial frame consists of one character of data bits with synchronization bits (start and stop bits), and an optional parity bit for error checking. note that this does not apply to spi operation (see section 19.4.2 ?spi frame formats? on page 216 ). the usart accepts all 30 combinations of the following as valid frame formats: ? 1 start bit ? 5, 6, 7, 8, or 9 data bits ? no, even or odd parity bit ? 1 or 2 stop bits a frame starts with the start bit followed by t he least significant data bi t and all data bits ending with the most significant bit. if enabled, the parity bit is inserted after the data bits, before the first stop bit. one frame can be directly followed by a start bit and a new frame, or the communication line can return to id le (high) state. figure 19-5 on page 215 illustrates the poss ible combinations of the frame formats. bits inside brackets are optional. figure 19-5. frame formats xck data setup (txd) data sample (rxd) xck data setup (txd) data sample (rxd) xck data setup (txd) data sample (rxd) xck data setup (txd) data sample (rxd) inven=0 inven=1 ucpha=0 ucpha=1 1 0 2 3 4 [5] [6] [7] [8] [p] st sp1 [sp2] (st / idle) (idle) frame
216 8077b?avr?06/08 xmega a 19.4.1 parity bit calculation even or odd parity can be selected for error checking. if even parity is selected, the parity bit is set to one if the number of data bits that is one is odd (making the total number of ones even). if odd parity is selected, the parity bit is set to one if the number of data bits that is one is even (making the total number of ones odd). 19.4.2 spi frame formats the serial frame in spi mode is defined to be one character of 8 data bits. the usart in master spi mode has two valid frame formats: ? 8-bit data with msb first ? 8-bit data with lsb first when a complete frame of 8 bits is transmitted, a new frame can directly follow it, or the commu- nication line returns to idle (high) state. 19.5 usart initialization usart initialization should use the following sequence: 1. set the txd pin value high, and optionally the xck pin low. 2. set the txd and optionally the xck pin as output. 3. set the baud rate and frame format. 4. set mode of operation (enables the xck pin output in synchronous mode). 5. enable the transmitter or the receiver depending on the usage. for interrupt driven usart operation, global interrupts should be disabled during the initialization. before doing a re-initialization with changed baud rate or frame format, be sure that there are no ongoing transmissions during the period the regi sters are changed. the transit and receive com- plete interrupt flags can be used to check that the transmitter has completed all transfers, and that there are no unread data in the receive buffer. 19.6 data transmission - the usart transmitter when the transmitter has been enabled, the normal port operation of the txd pin is overridden by the usart and given the function as the transmitter's serial output. the direction of the pin must be set as output using the direction register in the corresponding port. for details on port pin control refer to section 12. ?i/o ports? on page 114 . 19.6.1 sending frames a data transmission is initiated by loading the tr ansmit buffer (data) with the data to be sent. the data in the transmit buffer is moved to the shift register when the shift register is empty and ready to send a new frame. the shift register is loaded if it is in idle state (no ongoing table 1. st start bit, always low. (n) data bits (0 to 8). p parity bit. can be odd or even. sp stop bit, always high. idle no transfers on the communication line (rxd or txd). the idle state is always high.
217 8077b?avr?06/08 xmega a transmission) or immediately after the last stop bi t of the previous frame is transmitted. when the shift register is loade d with data, it will transfe r one comple te frame. the transmit complete interrupt flag (txcif) is set and the optional interrupt is generated when the entire frame in the shift register has been shifted out and there are no new data present in the transmit buffer. the transmit data register (data) can only be written when the data register empty flag (dreif) is set, indicating that the register is empty and ready for new data. when using frames with less than eight bits, the most significant bits written to the data are ignored. if 9-bit characters are used the ninth bit must be written to the txb8 bit before the low byte of the character is written to data. 19.6.2 disabling the transmitter a disabling of the transmitter w ill not become effective until on going and pending transmissions are completed, i.e. when the transmit shift register and transmit buffer register do not contain data to be transmitted. when transmitter is disabled it will no longer override the txdn pin and the pin direction is set as input. 19.7 data reception - the usart receiver when the receiver is enabled, the rxd pin is giv en the function as the receiver's serial input. the direction of the pin must be set as input, which is the default pin setting. 19.7.1 receiving frames the receiver starts data reception when it detects a valid start bit. each bit that follows the start bit will be sampled at the ba ud rate or xck clock, and shifted into the receive shift register until the first stop bit of a frame is received. a seco nd stop bit will be ignored by the receiver. when the first stop bit is received and a complete serial frame is present in the receive shift register, the contents of the shift register will be moved into the receive buffer. the receive complete interrupt flag (rxcif) is set, and the optional interrupt is generated. the receiver buffer can be read by reading the data register (data) location. data should not be read unless the receive complete interrupt flag is set. when using frames with less than eight bits, the unused most significant bits are read as zero. if 9-bit characters are used, the ninth bit must be read from the rxb8 bit before the low byte of the character is read from data. 19.7.2 receiver error flags the usart receiver has three error flags. the frame error (ferr), buffer overflow (bufovf) and parity error (perr) flags are accessible from the status register. the error flags are located in the receive fifo buffer together with their corresponding frame. due to the buffering of the error flags, the status register must be read before the receive buffer (data), since reading the data location changes the fifo buffer. 19.7.3 parity checker when enabled, the parity checker calculates the pa rity of the data bits in incoming frames and compares the result with the parity bit of the corresponding frame. if a parity error is detected the parity error flag is set.
218 8077b?avr?06/08 xmega a 19.7.4 disabling the receiver a disabling of the receiver will be immediate. the receiver buffer will be flushed, and data from ongoing receptions will be lost. 19.7.5 flushing the receive buffer if the receive buffer has to be flushed during normal operation, read the data location until the receive complete interr upt flags is cleared. 19.8 asynchronous data reception the usart includes a clock recovery and a data recovery unit for handling asynchronous data reception. the clock recovery logic is used for synchronizing the incoming asynchronous serial frames at the rxd pin to the internally generated baud rate clock. the data recovery logic sam- ples and low pass filters each incoming bit, ther eby improving the noise immunity of the receiver. the asynchronous reception operational range depends on the accuracy of the inter- nal baud rate clock, the rate of the incoming frames, and the frame size in number of bits. 19.8.1 asynchronous clock recovery the clock recovery logic synchronizes internal clock to the incoming serial frames. figure 19-6 on page 218 illustrates the sampling process of the start bit of an incoming frame. the sample rate is 16 times the baud rate for normal mode, and eight times the baud rate for double speed mode. the horizontal arrows illustrate the sy nchronization variation due to the sampling pro- cess. note the larger time variation when using the double speed mode of operation. samples denoted zero are samples done when the rxd li ne is idle, i.e. no co mmunication activity. figure 19-6. start bit sampling when the clock recovery logic detects a high (idle) to low (start) transition on the rxd line, the start bit detection sequence is initiated. sample 1 denotes the first zero-sample as shown in the figure. the clock recovery logic then uses samples 8, 9, and 10 for normal mode, and samples 4, 5, and 6 for double speed mode (indicated with sample numbers inside boxes on the figure) to decide if a valid start bit is received. if two or more of these three samples have a low level (the majority wins), the start bit is accepted. the clock recovery logic is synchronized and the data recovery can begin. if two or more of the three samples have a high level the start bit is rejected as a noise spike and the receiver starts looking for the next high to low-transition. the synchronization process is repeated for each start bit. 1234567 8 9 10 11 12 13 14 15 16 12 start idle 0 0 bit 0 3 123 4 5 678 12 0 rxd sample (u2x = 0) sample (u2x = 1)
219 8077b?avr?06/08 xmega a 19.8.2 asynchronous data recovery the data recovery unit uses sixteen samples in normal mode and eight samples in double speed mode for each bit. figure 19-7 on page 219 shows the sampling process of data and par- ity bits. figure 19-7. sampling of data and parity bit as for start bit detection, identical majority voting technique is used on the three center samples (indicated with sample numbers inside boxes) for deciding of the logic level of the received bit. this majority voting process acts as a low pass f ilter for the received signal on the rxd pin. the process is repeated for each bit until a complete frame is received. including the first, but exclud- ing additional stop bits. if the stop bit sampled has a logic 0 value, the frame error (ferr) flag will be set. figure 19-8 on page 219 shows the sampling of the stop bit in relation to the earliest possible beginning of the next frame's start bit. figure 19-8. stop bit sampling and ne xt start bit sampling a new high to low transition indicating the start bit of a new frame can come right after the last of the bits used for majority voting. for normal speed mode, the first low level sample can be at point marked (a) in stop bit sampling and next start bit sampling. for double speed mode the first low level must be delayed to (b). (c) marks a stop bit of full length at nominal baud rate. the early start bit detection influences the operational range of the receiver. 19.8.3 asynchronous operational range the operational range of the receiver is dependent on the mismatch between the received bit rate and the internally generated baud rate. if an external transmitter is sending on bit rates that are too fast or too slow, or the internally generated baud rate of the receiver does not match the external source?s base frequency, the receiver will not be able to synchroni ze the frames to the start bit. 1234567 8 9 10 11 12 13 14 15 16 1 bit n 123 4 5 678 1 rxd sample (u2x = 0) sample (u2x = 1) 1234567 8 9 10 0/1 0/1 0/1 stop 1 123 4 5 6 0/1 rxd sample (u2x = 0) sample (u2x = 1) (a) (b) (c)
220 8077b?avr?06/08 xmega a the following equations can be used to calculate the ratio of the incoming data rate and internal receiver baud rate. table 19-3 and table 19-4 on page 220 list the maximum receiver baud rate error that can be tolerated. normal speed mode has higher toleration of baud rate variations. table 1. table 1. d sum of character size and parity size (d = 5 to 10 bit). s samples per bit. s = 16 for normal speed mode and s = 8 for double speed mode. s f first sample number used for majority voting. s f = 8 for normal speed and s f = 4 for double speed mode. s m middle sample number used for majority voting. s m = 9 for normal speed and s m = 5 for double speed mode. r slow is the ratio of the slowest incoming data rate that can be accepted in relation to the receiver baud rate. r fast is the ratio of the fastest incoming data ra te that can be accepted in relation to the receiver baud rate. table 19-3. recommended maximum receiver baud rate error for normal speed mode (clk2x = 0) d #(data + parity bit) r slow (%) r fast (%) max total error (%) recommended max receiver error (%) 5 93.20 106.67 +6.67/-6.80 3.0 6 94.12 105.79 +5.79/-5.88 2.5 7 94.81 105.11 +5.11/-5.19 2.0 8 95.36 104.58 +4.58/-4.54 2.0 9 95.81 104.14 +4.14/-4.19 1.5 10 96.17 103.78 +3.78/-3.83 1.5 table 19-4. recommended maximum receiver baud rate error for double speed mode (clk2x = 1) d #(data + parity bit) r slow (%) r fast (%) max total error (%) recommended max receiver error (%) 5 94.12 105.66 +5.66/-5.88 2.5 6 94.92 104.92 +4.92/-5.08 2.0 7 95.52 104.35 +4.35/-4.48 1.5 r slow d 1 + () s s 1 ? ds ? s f ++ ------------------------------------------ - = r fast d 2 + () s d 1 + () ss m + ----------------------------------- =
221 8077b?avr?06/08 xmega a the recommendations of the maximum receiver baud rate error was made under the assump- tion that the receiver and transmitter equally divides the maximum total error. there are two possible sources for the receivers baud rate error. the receiver's system clock will always have some minor instability. in addition, the baud rate generator can not always do an exact division of the peripheral clock frequency to get the baud rate wanted. in this case the bsel and bscale value should be selected to give the lowe st possible error. 19.9 the impact of fractional baud rate generation fractional baud rate generation is possible for asynchronous operation due to the relatively high number of clock cycles (i.e. samples) for each frame. each bit is sampled sixteen times, but only the center samples are of importance. this leaves some slack for each bit. not only that, but the total number of samples for one frame is also relatively high. given a 1-start, 8-data, no-parity, and 1-stop bit frame format, and assumes that normal speed mode is used, the total number of samples for a frame is, (1+8+1)*16, or 160. as earlier stated, the uart can tolerate plus minus some samples. the critical factor is the time from the falling edge of the start bit (i.e. the clock synchronization) to the last bit's (i.e. the first stop bit) value is recovered. baud rate generators have the unwanted property of having large frequency steps between high baud rate settings. worst case is found between bsel value 0x000 and 0x001. going from an bsel value of 0x000 for which ha s a 10-bit frame of 160 sample s, to an bsel value 0x001 with 320 samples, shows a 50% change in frequency. however, when increasing the bsel values the step change will quickly decrease. ideally the step size should be small even between the fastest baud rates. this is where the advantage of the fractional baud rate generator emerges. in principle the fractional baud rate generator works by doing uneven counting and distributing the error evenly over the entire frame. a typical count sequence for an ordinary baud rate gener- ator is: 2, 1, 0, 2, 1, 0, 2, 1, 0, 2, ? which has an even period time. a baud rate clock tick each time the counter reaches zero, and a sample of the received signal on rxd is taken for each baud rate clock tick. for the fractional baud rate generator the count sequence can have an uneven period: 2, 1, 0, 3, 2, 1, 0, 2, 1, 0, 3, 2, ? in this example an extra cycle is added every se cond cycle. this gives a baud rate clock tick jit- ter, but the average period has been increased by a fraction, more prec isely 0.5 clock cycles. the impact of the fractional baud rate generation is that the step size between baud rate settings has been reduced. given a scale factor of -1 the worst-case step, then becomes from 160 to 240 samples per 10-bit frame compared to the previous from 160 to 320. higher negative scale fac- 8 96.00 103.90 +3.90/-4.00 1.5 9 96.39 103.53 +3.53/-3.61 1.5 10 96.70 103.23 +3.23/-3.30 1.0 table 19-4. recommended maximum receiver baud rate error for double speed mode (clk2x = 1) (continued) d #(data + parity bit) r slow (%) r fast (%) max total error (%) recommended max receiver error (%)
222 8077b?avr?06/08 xmega a tor gives even finer granularity. there is obviously a limit to how high the scale factor can be. a rule of thumb is that the value 2 bscale must be at least half of the minimum number of clock cycles a frame takes. for instance for 10-bit frames the minimum number of clock cycles is 160. this means that the highest applicable scale factor is -6 (2 -6 = 64 < 160/2 = 80). for higher bsel settings the scale factor can be increased. 19.10 usart in m aster spi mode using the usart in master spi mode (mspim) requires the transmitter to be enabled. the receiver can optionally be enabl ed to serve as the serial input. the xck pin will be used as the transfer clock. as for usart a data transfer is initiated by writin g to the data location. this is the case for both sending and receiving data since the transmitter c ontrols the transfer clock. the data written to data is moved from the transmit buffer to the shift register when the shift register is ready to send a new frame. the transmitter and receiver interrupt flags and corresponding usart interrupts in master spi mode are identical in function to the normal u sart operation. the receiver error status flags are not in use and is always read as zero. disabling of the usart transmitter or receiver in master spi mode is identical in function to the normal usart operation. 19.11 usart spi vs. spi the usart in master spi mode is fu lly compatible with the spi regarding: ? master mode timing diagram. ? the ucpha bit functionality is identical to the spi cpha bit. ? the udord bit functionality is identical to the spi dord bit. since the usart in master spi mode reuses the usart resources, the use of the usart in mspim is somewhat different compared to the xmega spi module. in addition to differences of the control register bits and no spi slave support, the following features differ between the two modules: ? the transmitter usart in master spi mode includes buffering. the xmega spi has no transmit buffer. ? the receiver in usart in master spi includes an additional buffer level. ? the spi wcol (write collision) bit is no t included in usart in master spi mode. ? the spi double speed mode (spi2x) bit is not included. however, the same effect is achieved by setting bsel accordingly. ? interrupt timing is not compatible. ? pin control differs due to the master only operation of the usart in master spi mode.
223 8077b?avr?06/08 xmega a a comparison of the usart in master spi mode and the spi pins is shown table 19-5 . 19.12 multi-processor communication mode enabling the multi-processor communication mode (mpcm) effectively reduces the number of incoming frames that has to be handled by th e receiver in a system with multiple mcus com- municating via the same serial bus. in this mode a dedicated bit in the frames is used to indicate whether the frame is an address or data frame. if the receiver is set up to receive frames that contain 5 to 8 data bits, the first stop bit is used to indicate the frame type. if the receiver is set up for frames with 9 data bits, the ninth bit is used. when the frame type bit is one, the frame contains an address. when the frame type bit is zero, the frame is a data frame. the transmitter is unaffected by the mpcm setting, but if 5- to 8-bit character frames are used, the transmitter must be set to use two stop bit since the first stop bit is used for indicating the frame type. if a particular slave mcu has be en addressed, it will receive th e following data frames as nor- mal, while the other slave mcus will ignore the received frames until another address frame is received. 19.12.1 using multi-processor communication mode for an mcu to act as a master mcu, it should use a 9-bit character frame format. the ninth bit must be set when an address frame is being transmitted and cleared when a data frame is being transmitted. the slave mcus must in this case be set to use a 9-bit character frame format. the following procedure should be used to exchange data in multi-processor communication mode: 1. all slave mcus are in multi- processor communication mode. 2. the master mcu sends an address frame, and all slaves receive and read this frame. 3. each slave mcu determines if it has been selected. 4. the addressed mcu will disable mpcm and re ceive all data frames. the other slave mcus will ignore the data frames. 5. when the addressed mcu has received the last data frame, it must enable mpcm again and wait for new address frame from the master. the process then repeats from 2. using any of the 5- to 8-bit character frame formats is possible, but impractical since the receiver must change between using n and n+1 character frame formats. this makes full duplex operation difficult since the transmitte r and receiver uses the same character size setting. table 19-5. comparison of usart in master spi mode and spi pins. usart spi comment txd mosi master out only rxd miso master in only xck sck functionally identical n/a ss not supported by usart in master spi
224 8077b?avr?06/08 xmega a 19.13 ircom mode of operation ircom mode can be enabled to use the ircom module with the usart. this enables irda 1.4 physical compliant modulation and demodulation for baud rates up to 115.2 kbps. for devices with more then one usart, ircom mode can only be enabled for one usart at the time. for details refer to ?ircom - ir communication module? on page 231 . 19.14 dma support dma support is available on the uart, usrt and spi master mode peripherals. for details on different usart dma transfer triggers refer to ?transfer triggers? on page 42 . 19.15 register d escription - usart 19.15.1 data - usart i/o data register the usart transmit data buffer register and usart receive data buffer registers share the same i/o address referred to as usart data register (data). the transmit data buffer reg- ister (txb) will be the destination for data written to the data register location. reading the data register location will retu rn the contents of the receiv e data buffer register (rxb). for 5-, 6-, or 7-bit char acters the upper unu sed bits will be ignored by the transmitter and set to zero by the receiver. the transmit buffer can only be written when the dreif flag in the status register is set. data written to data when the dreif flag is not set, will be ignored by the usart transmitter. when data is written to the transmit buffer, and the transmitter is enabled, the transmitter will load the data into the transmit shift register when the shift register is empty. the data is then transmitted on the txd pin. the receive buffer consists of a two level fifo. the fifo and the corresponding flags in the status register (status) will change state whenever the receive buffer is accessed (read). always read status before data in order to get the correct flags. 19.15.2 status - usart status register ? bit 7 - rxcif: usart receive complete interrupt flag this flag is set when there are unread data in the receive buffer and cleared when the receive buffer is empty (i.e., does not contain any unread data). when the receiver is disabled, the receive buffer will be fl ushed and consequently the rxcif will become zero. bit 76543210 +0x00 rxb[[7:0] txb[[7:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 +0x01 rxcif txcif dreif ferr bufovf perr - rxb8 status read/writerr/wrrrrrr/w initial value00100000
225 8077b?avr?06/08 xmega a when interrupt-driven data reception is used, the receive complete interrupt routine must read the received data from data in order to clear the rxcif. if not, a new interrupt will occur directly after the return from the current interrupt. this flag can also be cleared by writing a one to its bit location. ? bit 6 - txcif: usart transmit complete interrupt flag this flag is set when the entire frame in the transmit shift register has been shifted out and there are no new data in the transmit buffer (data). the txcif is automatically cleared when the transmit complete interrupt vector is executed. the flag can also be cleared by writing a one to its bit location. ? bit 5 - dreif: usart data register empty flag the dreif indicates if the transmit buffer (data) is ready to receive new data. the flag is one when the transmit buffer is empty, and zero when the transmit buffer contains data to be trans- mitted that has not yet been moved into the shift register. dreif is set after a reset to indicate that the transmitter is ready. always write this bit to zero when writin g the status register. dreif is cleared by writing data. when interrupt-driven data transmission is used, the data register empty interrupt routine must either wr ite new data to data in order to clear dreif or disable the data register empty interrupt. if not, a new interrupt will occur directly after the return from the current interrupt. ? bit 4 - ferr: frame error the ferr flag indicates the state of the first stop bit of the next readable frame stored in the receive buffer. the bit is set if the received character had a frame error, i.e. when the first stop bit was zero, and cleared when the stop bit of the received data is one. this bit is valid until the receive buffer (data) is read. the ferr is not affected by setting the sbmode bit in ctrlc since the receiver ignores all, except for the first stop bit. always write this bit location to zero when writing the status register. this flag is not used in master spi mode of operation. ? bit 3 - bufovf: buffer overflow the bufovf flag indicates data loss due to a receiver buffer full condition. this flag is set if a buffer overflow condition is detected. a buffer overflow occurs when the receive buffer is full (two characters), it is a new ch aracter waiting in the receive shift register, and a new start bit is detected. this flag is valid until the receive buffer (data) is read. always write this bit location to zero when writing the status register. this flag is not used in master spi mode of operation. ? bit 2 - perr: parity error if parity checking is enabled and the next character in the receive buffer has a parity error this flag is set. if parity check is not enabled the perr will always be read as zero. this bit is valid until the receive buffer (data) is read. always write this bit location to zero when writing the status register. for details on parity calculation refer to ?parity bit calculation? on page 216 . this flag is not used in master spi mode of operation. ? bit 1 - res: reserved this bit is reserved and will a lways be read as zero. for compat ibility with future devices, always write this bit to zero when this register is written.
226 8077b?avr?06/08 xmega a ? bit 0 - rxb8: receive bit 8 rxb8 is the ninth data bit of the received charac ter when operating with serial frames with nine data bits. when used, this bit must be read before reading the low bits from data. this bit unused in master spi mode of operation. 19.15.3 ctrla ? usart control register a ? bit 7:6 - res: reserved these bits are unus ed and reserved for future use. for compatibility with futu re devices, always write these bits to zero when this register is written. ? bit 5:4 - rxcintlvl[1:0]: receive complete interrupt level these bits enable the receive complete interrup t and select the interrupt level as described in ?interrupts and programmable multi-level interrupt controller? on page 108 . the enabled inter- rupt will be triggered when the rxci f in the status register is set. ? bit 3:2 - txcintlvl[1:0]: transmit complete interrupt level these bits enable the transmit complete interrupt and select the interrupt level as described in ?interrupts and programmable multi-level interrupt controller? on page 108 . the enabled inter- rupt will be triggered when the txci f in the status register is set. ? bit 1:0 - dreintlvl[1:0]: usart data register empty interrupt level these bits enable the data register empty inte rrupt and select the interrupt level as described in ?interrupts and programmable multi-level interrupt controller? on page 108 . the enabled inter- rupt will be triggered when the drei f in the status register is set. 19.15.4 ctrlb - usart control register b ? bit 7:5 - res: reserved these bits are unus ed and reserved for future use. for compatibility with futu re devices, always write these bits to zero when this register is written. ? bit 4 - rxen: receiver enable writing this bit to one enables the usart receiv er. the receiver will override normal port oper- ation for the rxd pin when enabled. disabling the receiver will flush the receive buffer invalidating the ferr, bufovf, and perr flags. bit 76543210 +0x03 - - rxcintlvl[1:0] txcintlvl[1:0] dreintlvl[1:0] ctrla read/write r r r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 +0x04 - - - rxen txen clk2x mpcm txb8 ctrlb read/write r r r r/w r/w r/w r/w r/w initial value00000000
227 8077b?avr?06/08 xmega a ? bit 3 - txen: transmitter enable writing this bit to one enables the usart tr ansmitter. the transmitter will override normal port operation for the txd pin when enabled. disabling the transmitter (writing txen to zero) will not become effective until ongoing and pending transmissions are completed, i.e., when the trans- mit shift register and transmit buffer register do not contain data to be transmitted. when disabled, the transmitter will no longer override the txd port. ? bit 2 - clk2x: double transmission speed writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively dou- bling the transfer rate for asynchronous co mmunication modes. for synchronous operation this bit has no effect and should always be written to zero. this bit is unused in master spi mode of operation. ? bit 1 - mpcm: multi-processor communication mode this bit enables the multi-processor communication mode. when the mpcm bit is written to one, the usart receiver ignores all the incoming frames that do not contain address informa- tion. the transmitter is unaffected by the mpcm setting. for more detailed information see ?multi-processor communication mode? on page 223 . this bit is unused in master spi mode of operation. ? bit 0 - txb8: transmit bit 8 txb8 is the ninth data bit in the character to be transmitted when operating with serial frames with nine data bits. when used this bit must be written before writing the low bits to data. this bit is unused in master spi mode of operation. 19.15.5 ctrlc - usart control register c note: 1. master spi mode ? bits 7:6 - cmode[1:0]: usart communication mode these bits select the mode of oper ation of the usart as shown in table 19-6 . bit76543210 +0x05 cmode[1:0] pmode[1:0] sbmode chsize[2:0] +0x05 (1) cmode[1:0] - - - udord ucpha - read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 1 1 0 table 19-6. cmode bit settings cmode[1:0] group configuration mode 00 asynchronous asynchronous usart 01 synchronous synchronous usart 10 ircom ircom (1) 1. see section 20. ?ircom - ir communication module? on page 231 for full description on using ircom mode. 11 mspi master spi (2) 2. see ?usart? on page 210 for full description of the ma ster spi mode (mspim) operation
228 8077b?avr?06/08 xmega a ? bits 5:4 - pmode[1:0]: parity mode these bits enable and set the type of parity generation according to table 19-7 on page 228 . when enabled, the transmitter will au tomatically generate and send the parity of the transmitted data bits within each frame. th e receiver will generate a parity value for the incoming data and compare it to the pmode setting and if a mismatch is detected, the perr flag in status will be set. these bits are unused in master spi mode of operation. ? bit 3 - sbmode: stop bit mode this bit selects the number of stop bits to be inserted by the transmitter according to table 19-8 on page 228 . the receiver ignores this setting. this bit is unused in master spi mode of operation. ? bit 2:0 - chsize[2:0]: character size the chsize[2:0] bits sets the number of data bits in a frame according to table 19-9 on page 228 . the receiver and transmitter use the same setting. ? bit 2 - udord: data order this bit sets the frame format. when written to one the lsb of the data word is transmitted first. when written to zero the msb of the data word is transmitted first. the receiver and transmitter table 19-7. pmode bits settings pmode[1:0] group configuration parity mode 00 disabled disabled 01 reserved 10 even enabled, even parity 11 odd enabled, odd parity table 19-8. sbmode bit settings sbmode stop bit(s) 01-bit 12-bit table 19-9. chsize bits settings chsize[2:0] group configuration character size 000 5bit 5-bit 001 6bit 6-bit 010 7bit 7-bit 011 8bit 8-bit 100 reserved 101 reserved 110 reserved 111 9bit 9-bit
229 8077b?avr?06/08 xmega a use the same setting. c hanging the setting of udord will co rrupt all ongoing communication for both receiver and transmitter. ? bit 1 - ucpha: clock phase the ucpha bit setting determine if data is samp led on the leading (first) edge or tailing (last) edge of xckn. refer to the ?spi clock generation? on page 214 for details. 19.15.6 baudctrla - usar t baud rate register ? bit 7:0 - bsel[7:0]: usart baud rate register this is a 12-bit value which contains the us art baud rate setting. the baudctrlb contains the four most significan t bits, and the baudctrla contains the eight least significant bits of the usart baud rate. ongoing transmissions by the transmitter and receiver will be corrupted if the baud rate is changed. writing baudctrla will trigger an immediate u pdate of the baud rate prescaler. 19.15.7 baudctrlb - usar t baud rate register ? bit 7:4 - bscale[3:0]: usart baud rate scale factor these bits select the baud rate generator scale factor. the scale factor is given in two's com- plement form from -7 (0b1001) to 7 (0b0111). the -8 (0b1000) setting is reserved. for positive scale values the baud rate generator is prescaled by 2 bscale . for negative values the baud rate generator will use fractional counting, wh ich increases the resolution. see equations in table 19-1 on page 213 . ? bit 3:0 - bsel[3:0]: usart baud rate register this is a 12-bit value which contains the us art baud rate setting. the baudctrlb contains the four most significan t bits, and the baudctrla contains the eight least significant bits of the usart baud rate. ongoing transmissions by the transmitter and receiver will be corrupted if the baud rate is changed. writing baudctrla will trigger an immediate u pdate of the baud rate prescaler. bit 76543210 +0x06 bsel[7:0] baudctrla read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 +0x07 bscale[3:0] bsel[11:8] baudctrlb read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0
230 8077b?avr?06/08 xmega a 19.16 register summary 19.16.1 register description - usart 19.16.2 register description - usart in master spi mode address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page +0x00 data data[7:0] 224 +0x01 status rxcif txcif dreif ferr bufovf perr - rxb8 224 +0x02 reserved - - - - - - - - +0x03 ctrla - - rxcintlvl[1:0] txcintlvl[1:0] dreintlvl[1:0] 226 +0x04 ctrlb - - - rxen txen clk2x mpcm txb8 226 +0x05 ctrlc cmode[1:0] pmode[1:0] sbmode chsize[2:0] 228 +0x06 baudctrla bsel[7:0] 230 +0x07 baudctrlb bscale[3:0] bsel[11:8] 229 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page +0x00 data data[7:0] 224 +0x01 status rxcif txcif dreif - - - - - 224 +0x02reserved--- ---- - +0x03 ctrla - - rxcintlvl[1:0] txcintlvl[1:0] dreintlvl[1:0] 226 +0x04 ctrlb - - - rxen txen - - - 226 +0x05 ctrlc cmode[1:0] - - - udord ucph - 227 +0x06 baudctrla bsel[7:0] 229 +0x07 baudctrlb bscale[3:0] bsel[11:8] 229
231 8077b?avr?06/08 xmega a 20. ircom - ir communication module 20.1 features ? pulse modulation/demodulation for infrared communication ? irda 1.4 compatible for baud rates up to 115.2 kbps ? selectable pulse modulation scheme ? 3/16 of baud rate period ? fixed pulse period, 8-bit programmable ? pulse modulation disabled ? built in filtering ? can be connected to and used by any usart 20.2 overview xmega contains an infrared communication module (ircom) irda 1.4 compatible module for baud rates up to 115.2 kbps. this supports three modulation schemes: 3/16 of baud rate period, fixed programmable pulse time based on the peripheral clock speed, or pulse modulation dis- abled. there is one ircom available, and th is can be connected to any usart to enable infrared pulse coding/decoding for that usart. figure 20-1. ircom connection to usarts and associated port pins the ircom is automatically enab led when a usart is set in ircom mode. when this is done signals between the usart and the rx/tx pins are routed through the module as shown in fig- ure 20-1 on page 231 . it is also possible to select an ev ent channel from the event system as input for the ircom receiver. this will di sable the rx input from the usart pin. ircom pulse decoding dif event system rxdnx txdnx usartxn .... usartc1 usartc0 rxdc1 txdc1 rxdc0 txdc0 pulse encoding decoded rxd encoded txd encoded rxd rxd... txd... decoded txd events
232 8077b?avr?06/08 xmega a for transmission, three pulse modulation schemes are available: ? 3/16 of baud rate period. ? fixed programmable pulse time based on the peripheral clock speed. ? pulse modulation disabled. for reception, a minimum high-level pulse width for the pulse to be decoded as a logical 0 can be selected. shorter pulses will then be discarded and the bit will be decoded to logical 1 as if no pulse where received. one ircom will be available for use with any u sart in the device. th e module can only be used in combination with one usart at a time, thus ircom mode must not be set for more than one usart at a time. this must be ensured in the user software. 20.2.1 event system filtering the event system can be used as the receiver input. this enables ircom or usart input from other i/o pins or sources than the corresponding rx pin. if event system input is enabled, input from the usart's rx pin is automatically disa bled. the event system has digital input filter (dif) on the event channels, that can be used for filtering. refer to ?event system? on page 56 ? for details on using the event system.
233 8077b?avr?06/08 xmega a 20.3 registers d escription - ircom 20.3.1 txplctrl - ircom transmitter pulse length control register ? bits 7:0 - txplctrl[7:0] - transmitter pulse length control the 8-bit value sets the pulse modulation scheme for the transmitter. setting this register will have no effect if ircom mode is not selected by a usart. by leaving this register value to zero, 3/16 of baud rate period pulse modulation is used. setting this value from 1 to 254 will give a fixed pulse length coding. the 8-bit value sets the number of system clock periods for the pulse. the start of the pulse will be synchronized with the rising edge of the baud rate clock. setting the value to 255 (0xff) will disable pul se coding, letting the rx and tx signals pass through the ircom module unaltered. this enables other features through the ircom module, such as half-duplex usart, loop-back testing and usart rx input from an event channel. 20.3.2 rxplctrl - ircom receiver pulse length control register ? bits 7:0 - rxplctrl[7:0] - receiver pulse length control the 8-bit value sets the filter coefficient for the ircom transceiv er. setting this register will have no effect if ircom mode is not selected by a usart. by leaving this register value to zero, filtering is disabled. setting this value between 1 and 255 will enable filtering, where x+ 1 equal samples is required fo r the pulse to be accepted. 20.3.3 ctrl - ircom control register ? bits 7:4 - res: reserved these bits are unus ed and reserved for future use. for compatibility with futu re devices, always write these bits to zero when this register is written. bit 76543210 +0x00 txplctrl[7:0] txplctrl read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 00000000 bit 76543210 +0x01 rxplctrl[7:0] rxplctrl read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 00000000 bit 76543210 +0x02 - - - - evsel[3:0] ctrl read/write r r r r r/w r/w r/w r/w initial value 00000000
234 8077b?avr?06/08 xmega a ? bits 3:0 - evsel [3:0]: event channel selection these bits select the event channel source for the ircom receiver, according to table 20-1 on page 234 . if event input is selected for the ircom receiver, the input from the usart?s rx pin is automatically disabled. 20.4 register summary - ircom table 20-1. event channel select evsel[3:0] group configuration event source 0000 none 0001 (reserved) 0010 (reserved) 0011 (reserved) 0100 (reserved) 0101 (reserved) 0110 (reserved) 0111 (reserved) 1xxx chn event system channelx; x = {0, ?,7} address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page +0x00 txplctrl txplctrl[7:0] 233 +0x01 rxplctrl rxplctrl[7:0] 233 +0x02 ctrl - evsel[3:0] 233
235 8077b?avr?06/08 xmega a 21. crypto engines 21.1 features ? data encryption standard (des) core instruction ? advanced encryption stan dard (aes) crypto module ? des instruction ? encryption and decryption ? des supported ? single-cycle des instruction ? encryption/decryption in 16 clock cycles per 8-byte block ? aes crypto module ? encryption and decryption ? support 128-bit keys ? support xor data load mode to the state memory ? encryption/decryption in 375 clock cycles per 16-byte block 21.2 overview the advanced encrypti on standard (aes) and da ta encryption standar d (des) are two com- monly used standa rds for encryption. these are suppor ted through an aes peripheral module and a des core instruction. des is supported by a des instruction in the avr xmega core. the 8-byte key and 8-byte data blocks must be loaded into the register file, and then des must be executed 16 times to encrypt/decrypt the data block. the aes crypto module encrypts and decrypts 128-bit data blocks with the use of a 128-bit key. the key and data must be loaded into the module before encryption/decryption is started. it takes 375 peripheral clock cycles before encrypted/decrypted data can be read out. 21.3 des instruction the des instruction is a single cycle instructio n, that needs to be executed 16 times subse- quently in order to decrypt or encrypt an 64-bit (8 bytes) data block. the data and key blocks must be loaded into the register file before encryption/decryption is started. the 64-bit data block (plaintext or ciphertext) is placed in registers r0-r7, where lsb of data is placed in lsb of r0 and msb of data is placed in msb of r7. the full 64-bit key (includ- ing parity bits) is placed in registers r8-r15, with lsb of key in lsb of r8 and msb of key in msb of r15.
236 8077b?avr?06/08 xmega a figure 21-1. register file usage during des encryption/decryption. executing one des instruction performs one round in the des algorithm. sixteen rounds must be executed in increasing order to form the correct des ciphertext or plaintext. intermediate results are stored in the register file (r0-r15) after each des instruction. after sixteen rounds the key is located in r8-r16 and the encrypted/decrypted ciphertext/plaintext is located in r0- r7. the instruction's operand (k) determines which round is executed, and the half carry flag (h) in the cpu status register determines whether encryption or decryption is performed. if the half carry flag is set, decryption is performed and if the flag is cleared, encryption is performed. for more details on the de s instruction refe r to the avr instruction set manual. 21.4 aes crypto module the aes crypto module performs encryption and decrypt ion according to th e advanced encryp- tion standard (fips-197). the 128-bit key block and 128-bit data block (plaintext or ciphertext) must be loaded into the key and state memory in the aes cryp to module. this is done by writ- ing the aes key register and state register sequentially with 16 bytes. it is selectable from software whether the modul e should perform encryption or decryption. it is also possible to enable xor mo de where all new data loaded to the state key is xor?ed with the current data in the state memory. the aes module uses 375 clock cycles before the encrypted/decrypted ciphertext/plaintext is available for readout in the state memory. register file r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 ... r31 data0 data1 data2 data3 data4 data5 data6 data7 key0 key1 key2 key3 key4 key5 key6 key7 data key
237 8077b?avr?06/08 xmega a the following procedure for setup and use is recommended: 1. enable aes interrupts (optional) 2. select the aes direction, encryption or decryption. 3. load the key data block into the aes key memory 4. load the data block into the aes state memory 5. start the encryption/decryption operation if more than one block is to be encrypted or decrypted repeat the procedure from step 3. when the encryption/decryption procedure is complete the aes interrupt flag is set and the optional interrupt is generated. 21.4.1 key and state memory the aes key and state memory are both 16 x 8- bit memories that are accessible through the key (key) and state (state ) register, respectively. each memory has two 4-bit address pointers used to address the memory for read and write, respectively. the initial value of the pointers are zero. after a read or write operation to the state or key register, the appropriate pointer is automatically incremented. accessing (read or write) the control register (ctrl) will reset all pointers to zero. a pointer overfl ow (a sequential read or write is done more than 16 times) will also se t the affected pointer to zero. the address point- ers are not accessible from software. read and write memory pointers are both incremented during write operations in xor mode. access to the key and state registers are onl y possible when encryption/decryption is not in progress. figure 21-2. the state memory with pointers and register 4-bit state write address pointer 1 - 14 15 state 0 4-bit state read address pointer reset pointer reset pointer reset or access to aes control reset or access to aes control state[read pointer] xor xor i/o data bus
238 8077b?avr?06/08 xmega a the state memory contains the aes state thro ughout the encryption/decryption process. the initial value of the state is the in itial data (i.e. plain text in the encryption mode, and cipher text in the decryption mode). the last value of the state is the encrypted/decrypted data. figure 21-3. the key memory with pointers and register. in the aes crypto module the following definit ion of the key is used: ? in encryption mode, the key is th e one defined in the aes standard. ? in decryption mode, the key is the last subk ey of the expanded key defined in the aes standard. in decryption mode the key expansion procedure must be executed by software before opera- tion with the aes crypto module, so that the last su bkey is ready to be loaded through the key register. alternatively this pr ocedure can be run by hardware by using the aes crypto module and process a dummy data block in encryption mode, using the same key. after the end of the encryption, reading from the key memory allows to obtain the last subkey, i.e. get the result of the key expansion procedure. table 21-1 on page 238 shows the results of reading the key, depending on the mode (encryption or decryption) and status of the aes crypto module. table 21-1. the result of reading the key memory at different stages. 21.4.2 dma support the aes module can trigger a dma transfer when encryption/decryption pr ocedure is complete. fore more details on dma transfer triggers, refer to ?transfer triggers? on page 42 . encryption decryption before data processing after data processing before data processing after data processing same key as loaded the last subkey generated from the loaded key same key as loaded the initial key generated form the last loaded subkey. 4-bit key write address pointer 1 - 14 15 key 0 4-bit key read address pointer reset pointer reset pointer reset or access to ctrl reset or access to ctrl
239 8077b?avr?06/08 xmega a 21.5 register d escription - aes 21.5.1 ctrl - aes control register ? bit 7 - start: aes start/run setting this bit starts the encryption/decryption procedure, and this bit remains set while the encryption/decryption is ongoing. writing this bit to ze ro will stop/abort any ongoing encryp- tion/decryption process. this bit is automatically cleared if the srif or the error flag in status is set. ? bit 6 - auto: aes auto start trigger setting this bit enables the auto start mode. in auto start mode the start bit will trigger auto- matically and start the encryption/decryption when the following conditions are met: ? the auto bit is set before the state memory is loaded. ? all memory pointers (state read/write and key read/write) are zero. ? state memory is fully loaded. if not will the encryption/ decryption be started with an incorrect key. ? bit 5 - reset: aes software reset setting this bit will reset the aes crypto module to its initial status on the next positive edge of the peripheral clock. all registers, pointers and memories in the module are set to their initial value. when written to one, the bit stays high fo r one clock cycle before it is reset to zero by hardware. ? bit 4 - decrypt: aes de cryption / direction this bit sets the direction for the aes crypto module. writing th is bit to zero will set the module in encryption mode. writing one to this bit sets the module in decryption mode. ? bit 3 - res: reserved this bit is unused and reserved fo r future use. for comp atibility with future devices, always write this bit to zero when this register is written. ? bit 2 - xor: aes state xor load enable setting this bit enables xor data load to the st ate memory. when this bit is set the data loaded to the state memory is bitwise xor'ed with current data in the state memory. writing this bit to zero disables xor load mode, thus new data written to the state memory overwrites the current data in the state memory. bit 76543210 +0x00 start auto reset decrypt - xor - - ctrl read/write r/w r/w r/w r/w r r/w r r initial value00000000
240 8077b?avr?06/08 xmega a ? bit 1:0 - res: reserved these bits are unus ed and reserved for future use. for compatibility with futu re devices, always write these bits to zero when this register is written. 21.5.2 status - aes status register ? bit 7 - error: aes error the error flag indicates an ille gal handling of the aes crypto mo dule. the flag is set in the following cases: ? setting start in the control register while the state memory and/or key memory are not fully loaded or read. this error occurs when the total number of read/write operations from/to the state and key register is not a multiple of 16 before an aes start. ? accessing (read or write) the contro l register while the start bit is one. this flag can be cleared by software by writing one to its bit location. ? bit 6:1 - res: reserved these bits are reserved and will always be read as zero. for compatibility with future devices, always write these bits to zero when this register is written. ? bit 0 - srif: aes state ready interrupt flag this flag is the interrupt/dma request flag and is set when the encrypti on/decryption procedure is completed and the state memory contains valid data. as long as the flag is zero this indicates that there is no valid encrypted/decrypted data in the state memory. the flag is cleared by hardware when a read acce ss is made to the state memory (the first byte is read). alternatively the bit can be cleared by writing a one to its bit location 21.5.3 state - aes state register the state register is used to access the stat e memory. before encryption/decryption can take place the state memory must be written sequentially byte by byte through the state register. after encryption/decryption is done the ciphertext/p laintext can be read sequentially byte by byte through the state register. loading the initial data to the state register should be made after setting the appropriate aes- mode and direction. during encryption/ decryption this register can not be accessed. bit 76543210 +0x01 error------srifstatus read/writerrrrrrrr initial value00000000 bit 76543210 +0x02 state state read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0
241 8077b?avr?06/08 xmega a 21.5.4 key - aes key register the key register is used to access the key memory. before encryption/decryption can take place the key memory must be written sequentially byte by byte through the key register. after encryption/decryption is done the last subkey can be read sequentially byte by byte through the key register. loading the initial data to the key register should be made after setting the appropriate aes- mode and direction. 21.5.5 intctrl - aes interrupt control register ? bit 7:2 - res: reserved these bits are unus ed and reserved for future use. for compatibility with futu re devices, always write these bits to zero when this register is written. ? bit 1:0 - intlvl[1:0]: aes interrupt priority and enable these bits enable the aes interrupt and se lect the interrupt le vel as described in ?interrupts and programmable multi-level interrupt controller? on page 108 . the enabled interrupt will be trig- gered when the srif in the status register is set. bit 76543210 +0x03 key key read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 7654321 0 +0x04 - - - - - - intlvl[1:0] intctrl read/writerrrrrrr/wr/w initial value 0 0 0 0 0 0 0 0
242 8077b?avr?06/08 xmega a 21.6 register summary - aes address name bit 7 bit 6 bit 5 bit 4 b it 3 bit 2 bit 1 bit 0 page +0x00 ctrl start auto reset decrypt - xor - - 239 +0x01 status error - - - - - - srif 240 +0x02 state state[7:0] 240 +0x03 key key[7:0] 241 +0x04 intctrl - - - - - - intlvl[1:0] 241 +0x05 reserved - - - - - - - - +0x06 +0x07 +0x08 +0x09 +0x0a +0x0b +0x0c +0x0d +0x0e +0x0f
243 8077b?avr?06/08 atxmega 22. ebi - external bus interface 22.1 features ? supports sram up to ? 512k bytes using 2-port ebi ? 16m bytes using 3-port ebi ? supports sdram up to ? 128m bit using 3-port ebi ? four software configurable chip selects ? software configurable wait state insertion ? clocked from the fast peripheral clock at two times the cpu speed 22.2 overview the external bus interface (ebi) is the interf ace for connecting external peripheral and memory to access it through the data memory space. when the ebi is enabled, data address space out- side the internal sram becomes av ailable using dedicated ebi pins. the ebi can interface external sram, sdram, and/or peripherals such as lcd displays and other memory mapped devices. the address space, and the number of pins used for the external memory is selectable from 256 bytes (8-bit) and up to 16m bytes (24-bit). various multiplexing modes for address and data lines can be selected for optimal use of pins when more or less pins are available for the ebi. the complete memory will be mapped in to one linear data ad dress space continuing from the end of the internal sram, refer to ?data memory? on page 21 for details on this. the ebi has four chip selects with separate c onfiguration. each can be configured for sram, sram low pin count (lpc) or sdram. the ebi is clocked from the fast peripheral cloc k, running up to two times faster than the cpu and supporting speeds of up to 64 mhz. for sdram both 4-bit and 8-bit sdram is suppo rted, and sdram configurations such as cas latency and refresh rate is configurable in software. for more details on sram and sdram, and how these memory types are organized and work, refer to sram and sdram specific documentation and data sheets. this section only contains ebi specific details. 22.3 chip select the ebi module has four chip select lines (cs0 to cs3) where each can be associated with separate address ranges. the chip selects control which memory or memory mapped external hardware that is accessed when a given memory address is issued on the ebi. each chip select has separate configuration, and can be configured for sram or sram low pin count (lpc). chip select 3 can also be configured for sdram. the data memory address space associated for each chip select is decided by a configurable base address and address size for each chip select. 22.3.1 base address the base address is the lowest address in the address space for a chip select. this decides the first location in data memory space where t he connected memory hardware can be accessed.
244 8077b?avr?06/08 atxmega the base address associated with each chip select must be on a 4 kbyte boundary, i.e to address 0, 4096, 8192 etc. 22.3.2 address size the address size selects how many bits of the address that should be compared when generat- ing a chip select. the address size can be anything from 256 bytes to 16m bytes. if the address space is set to anything larger than 4k bytes, the base address must be on a boundary equal to the address space. with 1m byte address space for a chip select, the base address must be on a 0, 1m byte, 2m byte etc. boundary. if the ebi is configured so that if the address spaces overlap, the internal memory space have priority, followed by chip sele ct 0 (cs0), cs1, cs2 and cs3. 22.3.3 chip select as address lines if one or more chip select lines are unused, they can in some combinations be used as address lines instead. this can enable larger external memory or external cs generation. each column in figure 22-1 on page 244 shows enabled chip select lines (csn), and the address lines avail- able on unused chip select lines (ann). column four shows that all four cs lines are used as address lines when only cs3 is enabled, and this is for sdram configuring. figure 22-1. chip select and address line combinations 22.4 i/o pin configuration when the ebi is enabled it will ov erride the direction and/or value for the i/o pins where the ebi lines are placed. the ebi will override the directio n and value for the i/o pins wher e the ebi data lines are placed. the ebi will only override value, but not direction for the i/o pins where the ebi address and control lines are placed. these i/o pins must be configured to output when the ebi is used. i/o pins for unused ebi address and control lines can be used as normal i/o pins or for other alter- nate functions on the pins. for control signals that are active-low, the pin output value should be set to one (high). for con- trol signals that are active-high, pin output value should be set to zero (low). address lines does not requires specific pin output value configuration. the chip select lines should have pull-up resi stors to ensure that these are kept high during power-on and reset. for more details on i/o pin configuration refer to ?i/o ports? on page 114 . cs3 cs2 cs1 cs0 cs3 cs2 cs1 a16 cs3 cs2 a17 a16 a19 a18 a17 a16
245 8077b?avr?06/08 atxmega 22.5 ebi clock the ebi is clocked from the peripheral 2x (clk 2per ) clock. this clock can run at the cpu clock frequency, but it can also run at two times the cpu clock frequency. this can be used to lower the ebi access time. refer to ?system clock and clock options? on page 67 for details the peripheral 2x clock and how to configure this. 22.6 sram configuration for use with sram the ebi can be configured for various address multiplexing modes by using external address latches, or with no multiplexing. when a limited number of pins on the device are is available for the ebi, address latch enable (ale) signals are used to control external latches that multiplex address lines from the ebi. the available configurations is shown in sec- tion 22.6.1 on page 245 through section 22.6.4 on page 246 . table 22-1 on page 245 describe the sram interface signals. 22.6.1 no multiplexing when no multiplexing is used, there is a one- to-one connection between the ebi and the sram. no external address latches are used. figure 22-2. non-multiplexed sram connection 22.6.2 multiplexing address byte 0 and 1 when address byte 0 (a[7:0]) and address byte 1 (a15:8]) are multiplexed, they are output from the same port, and the ale1 signal from the device control the address latch. table 22-1. sram interface signals signal description cs chip select we write enable re read enable ale[2:0] address latch enable a[23:0] address d[7:0] data bus ad[7:0] combined address and data ebi sram d[7:0] a[7:0] d[7:0] a[7:0] a[15:8] a[21:16] a[15:8] a[21:16]
246 8077b?avr?06/08 atxmega figure 22-3. multiplexed sram connection using ale1 22.6.3 multiplexing address byte 0 and 2 when address byte 0 (a[7:0]) and address byte 2 (a23:16) are multiplexed, they are output from the same port, and the ale2 signal from the device control the address latch. figure 22-4. multiplexed sram connection using ale2 22.6.4 multiplexing address byte 0, 1and 2 when address byte 0 (a[7:0]), address byte 1 (a15:8]) and address byte 2 (a23:16] are multi- plexed, they are output from the same port, and the ale1 and ale2 signal from the device control the external address latches. ebi sram d[7:0] a[15:8]/ a[7:0] ale1 d q g d[7:0] a[7:0] a[15:8] a[19:16] a[19:16] ebi sram d[7:0] a[23:16]/ a[7:0] ale2 d q g d[7:0] a[7:0] a[15:8] a[23:16] a[15:8]
247 8077b?avr?06/08 atxmega figure 22-5. multiplexed sram connecti on using ale1 and ale2 22.6.5 address latch requirements the address latch timing and parameter requirements are described in ?ebi timing - tbd? on page 252 . 22.6.6 timing sram or external memory devices may have diffe rent timing requirements. to meet these vary- ing requirements, each chip select can be configured with different wait-states. timing details is described in ?ebi timing - tbd? on page 252 . 22.7 sram lpc configuration the sram low pin count (lpc) configuration enables ebi to be configured for multiplexing modes where the data and address lines are mult iplexed. compared to sram configuration, this can further reduce the number of pins required for the ebi. the available configurations is shown in section 22.7.1 on page 247 through section 22.7.2 on page 248 timing and address latch requirements is as for sram configuration. 22.7.1 multiplexing data with address byte 0 when the data byte and address byte 0 (ad[7:0]) are multiplexed, they are output from the same port, and the ale1 signal from the device controls the address latch. figure 22-6. multiplexed sram lpc connection using ale1 ebi sram d[7:0] a[23:16]/ a[15:8]/ a[7:0] ale1 ale2 d q g d q g d[7:0] a[7:0] a[15:8] a[23:16] ebi sram ad[7:0] ale1 d q g d[7:0] a[7:0] a[15:8] a[19:16] a[19:16] a[15:8]
248 8077b?avr?06/08 atxmega 22.7.2 multiplexing data with address byte 0 and 1 when the data byte and address byte 0 (ad[7:0]), and address byte 1 (a15:8]) are multiplexed, they are output from the same port, and the ale1 and ale2 signal from the device control the external address latches. figure 22-7. multiplexed sram lpc connec tion using ale1 and ale2 22.8 sdram configuration chip select 3 on the ebi can be configured from sdram operation, and the ebi must be config- ured for 3-port or 4-port interface. the sdram can be configured for 4-bit or 8-bit data bus, and 4-port interface must be used for 8-bit data bus. the sdram interface signals from the ebi to the sdram is listed in table 22-2 on page 248 . ebi sram a[15:8]/ ad[7:0] ale1 ale2 d q g d q g d[7:0] a[7:0] a[15:8] a[19:16] a[19:16] table 22-2. sdram interface signals signal description cs chip select we write enable ras row address strobe cas column address strobe dqm data mask signal/ output enable cke clock enable clk clock ba[1:0] bank address a[12:0] address bus a[10] precharge d[7:0] data bus
249 8077b?avr?06/08 atxmega 22.8.1 supported commands the sdram commands that are supported by the ebi is listed in table 22-3 on page 249 . 22.8.2 3-port ebi configuration when 3 ebi ports are available, sdram can be connected with 3-port ebi configuration. when this is done only 4-bit data bus is available, and any chip select must be controlled from software using a general purpose i/o pin (pxn). figure 22-8. 3-port sdram configuration 22.8.3 4-port ebi configuration when 4 ebi ports are available, sdram can be connected with 3-port or 4-port ebi configura- tion. when 4-port configuration is used, 8-bit data bus is available and all four chip selects will be available. table 22-3. supported sdram commands command description nop no operation active activate the selected bank and select the row. read input the starting column address and begin the burst read operation. write input the starting column address and begin the burst write operation. precharge deactivate the open row of selected bank or all banks auto refresh refresh one row of each bank load mode self refresh activate self refresh mode ebi sdram we cas/re ras dqm clk cke ba[1:0] pxn d[3:0] a[7:0]] we cas ras dqm clk cke cs ba[1:0] a[7:0] d[3:0] a[11:8] a[11:8]
250 8077b?avr?06/08 atxmega figure 22-9. 4-port sdram configuration 22.8.4 timing the clock enable (cke) signal is required for s dram when the ebi is clocked at 2x the cpu clock speed. 22.8.5 initialization configuring chip select 3 to sdram will enabl e the initialization of the sdram. the ?load mode register? command is automatical ly issued at the end of the initialization. for the correct information to be loaded to the sdram, one must do one of the following: 1. configure sdram control registers before enabling chip select 3 to sdram. 2. issue a ?load mode register? command and perform a dummy-access after sdram is initialized. the sdram initialization is non-interruptible by other ebi accesses. 22.8.6 refresh the ebi will automatically handle the refresh of the sdram as long as the refresh period is con- figured. refresh will be done as soon as avail able after the refresh counter reaches the period. the ebi can collect up to 4 refresh commands in case the interface is busy on another chip select or in the middle of a read/write at the time a refresh should have been performed. 22.9 combined sram & sdr am configuration combined sram and sdram configuration enables the ebi to have both sdram and sram connected at the same time. this only avail able for devices with 4 port ebi interface. figure 22- 10 on page 251 shows the configuration with all interface signals. ebi sdram we cas/re ras dqm clk cke ba[1:0] cs[3:0] d[7:0] a[7:0]] we cas ras dqm clk cke cs ba[1:0] a[7:0] d[7:0] a[11:8] a[11:8]
251 8077b?avr?06/08 atxmega figure 22-10. combined sram and sdram connection ebi sdram sram we cas/re ras/ale1 dqm clk cke ba[1:0] cs[3:0] d[7:0] a[7:0]/a[15:8] we cas ras dqm clk cke cs ba[1:0] a[7:0] d[7:0] d q g a[11:8]/a[19:16] a[11:8] a[7:0] a[15:8] d[7:0] we cs re a[19:16]
252 8077b?avr?06/08 atxmega 22.10 ebi timing - tbd 22.10.1 sram 22.10.1.1 sram, non-multiplexed address -tbd 22.10.1.2 sram, multiplexed address, 1x clock mode - tbd 22.10.1.3 sram, multiplexed address, 2x clock mode - tbd 22.10.1.4 sram lpc, multiplexed address and data, 1x clock mode - tbd 22.10.1.5 sram, lpc, multiplexed address and data, 2x clock mode - tbd table 22-4. ebi sram characteristics 1x clock mode 2x clock mode symbol parameter min. max min. max unit 1/ t clk oscillator frequency t alh address hold after ale low ns t als address setup before ale low (read and write) ns t alw ale width ns t arh address hold after re high ns t awh address hold after we high ns t ars address setup before re high ns t aws address setup before we low ns t drh data hold after re high ns t dwh data hold after we high ns t drs data setup to re high ns t dws data setup to we high ns t rdd read low to data valid ns t rw read enable pulse width ns t ww write enable pulse width ns t csh chip select hold ns t css chip select setup ns
253 8077b?avr?06/08 atxmega 22.10.2 sdram 22.10.2.1 4-bit, 1x clock mode - tbd 22.10.2.2 8-bit, 2x clock mode - tbd table 22-5. ebi sdram characteristics symbol parameter 1x clock mode 2x clock mode min max min max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
254 8077b?avr?06/08 atxmega 22.11 register description - ebi 22.11.1 ctrl - ebi control register ? bit 7:6 - sddataw[1:0]: ebi sdram data width setting these bits select the ebi sdram data width configuration according to table 22-6 on page 254 . ? bit 5:4 - lpcmode[1:0]: ebi sram low pin-count mode these bits select the ebi sram lpc configuration according to table 22-7 on page 254 ? bit 3:2 - srmode[1:0]: sram mode these bits selects the ebi sram configuration according to table 22-8 on page 254 . bit 76543210 +0x00 sddataw[1:0] lpcmode[1:0] srmode[1:0] ifmode[1:0] ctrl read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 22-6. sdram mode sddataw[1:0] group configuration description 00 4bit 4 bit data bus 01 8bit (1) 1. 8-bit data bus only available for 4-port ebi interface 8 bit data bus 10 - reserved 11 - reserved table 22-7. sram lpc mode lpcmode[1:0] group configuration ale description 00 ale1 ale1 data multiplexed with address byte 0 01 - - reserved 10 ale12 (1) 1. ale12 is not available for 2-port ebi interface. ale1 & 2 data multiplexed with address byte 0 and 1 11 - - reserved table 22-8. sram mode srmode[1:0] group configuration ale description 00 ale1 ale1 address byte 0 and 1 multiplexed 01 ale2 (1) ale2 address byte 0 and 2 multiplexed 10 ale12 (1) 1. ale2 and noale only availabl e with 4-port ebi interface ale1 & 2 address byte 0, 1 and 2 multiplexed 11 noale no ale no address multiplexing
255 8077b?avr?06/08 atxmega ? bit 1:0 - ifmode[1:0]: ebi interface mode these bits select ebi interface mode and the number of ports that should be enabled and over- ridden for ebi, according to table 22-9 on page 255 . 22.11.2 sdramctrla - sdra m control register a ? bit 7:4 - res: reserved these bits are reserved and will always be read as zero. ? bit 3 - sdcas: sdram cas latency this bit sets the cas latency as a number of peripheral 2x clock cycles. by default this bit is zero and the cas latency is two peripheral 2x clock cycles. when this bit is set to one the cas latency is three peripheral 2x clock cycles. ? bit 2 - sdrow: sdram row bits this bits sets the number of row bits used for t he connected sdram. by default this bit is zero, and, the row bit setting is set to 12 row bits. when this bit is set to one the row bit setting is set to 13 row bits. ? bit 1:0 - sdcol[1:0]: sdram column bits these bits select the number of column bits th at are used for the connected sdram according to table. table 22-10 on page 255 . table 22-9. ebi mode ifmode[1:0] group configuration description 00 disabled ebi disabled 01 3port ebi enabled with 3-port interface 10 4port ebi enabled with 4-port interface 11 2port ebi enabled with 2-port interface bit 7654 3 2 10 +0x01 ----sdcassdrowsdcol[1:0]s dramctrla read/write r r r r r/w r/w r/w r/w initial value0000 0 0 00 table 22-10. sdram column bits sdcol[1:0] group conf iguration description 00 8bit 8 column bits 01 9bit 9 column bits 10 10bit 10 column bits 11 11bit 11 column bits
256 8077b?avr?06/08 atxmega 22.11.3 refresh - sdram refresh period register ? bit 15:10 - res: reserved these bits are reserved and will always be read as zero. ? bit 9:0 - refresh[9:0]: sdram refresh period this register sets the refresh period as a number of peripheral 2x clock (clk per2 ) cycles. if the ebi is busy with another external memory acce ss at time of refresh, up to 4 refresh will be remembered and given at the first available time. 22.11.4 initdly - sdram initialization delay register ? bit 15:14 - res: reserved these bits are reserved and will always be read as zero. ? bit 13:0 - initdly[13:0]: sdram initialization delay this register is used to delay the initialisa tion sequence after the controller is enabled until all voltages are stabilized and the sdram clock has been running long enough to take the sdram chip through its initialisation se quence. the initialisation sequence includes pre-charge all banks to their idle state issuing an auto-refresh cycle and t hen loading the mode register. the setting in this register is as a number of peripheral 2x clock cycles. 22.11.5 sdramctrlb - sdra m control register b bit 7654 3 2 10 +0x04 refresh[7:0] refreshl +0x05 ---- - -refresh[9:8]refreshh 15 14 13 12 11 10 9 8 read/write r/w r/w r/w r/w r/w r/w r/w r/w rrrr r rr/wr/w initial value0000 0 0 00 0000 0 0 00 bit 7654 3 2 10 +0x06 initdly[7:0] initdlyl +0x07 - - initdly[9:8] initdlyh 15 14 13 12 11 10 9 8 read/write r/w r/w r/w r/w r/w r/w r/w r/w r r r/w r/w r/w r/w r/w r/w initial value0000 0 0 00 0000 0 0 00 bit 7654 3 2 10 +0x08 mrdly[1:0] rowcycdly[2:0] rpdly[2:0] sdramctrlb read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value0000 0 0 00
257 8077b?avr?06/08 atxmega ? bit 7:6 - mrdly[1:0]: s dram mode register delay these bits select the delay between mode register command and an activate command in number of peripheral 2x clock (clk per2 ) cycles, according to table 22-11 on page 257 . ? bit 5:3 - rowcycdly[2:0]: sdram row cycle delay these bits select the delay between a refresh and an activate command in number of periph- eral 2x clock (clk per2 ) cycles, according to table 22-12 on page 257 .. ? bit 2:0 - rpdly[2:0]: sdram row to pre-charge delay rpdly defines the delay between a pre-charge command and another command in number of peripheral 2x clock (clk per2 ) cycles, according to table 22-13 on page 257 . table 22-11. sdram column bits settings mrdly[1:0] group configuration description 00 0clk 0 clk per2 cycles delay 01 1clk 1 clk per2 cycles delay 10 2clk 2 clk per2 cycles delay 11 3clk 3 clk per2 cycles delay table 22-12. sdram row cycle delay settings rowcydly[2:0] group configuration description 000 0clk 0 clk per2 cycles delay 001 1clk 1 clk per2 cycles delay 010 2clk 2 clk per2 cycles delay 011 3clk 3 clk per2 cycles delay 100 4clk 4 clk per2 cycles delay 101 5clk 5 clk per2 cycles delay 110 6clk 6 clk per2 cycles delay 111 7clk 7 clk per2 cycles delay table 22-13. sdram row cycle delay settings rpdly[2:0] group configuration description 000 0clk 0 clk per2 cycles delay 001 1clk 1 clk per2 cycles delay 010 2clk 2 clk per2 cycles delay 011 3clk 3 clk per2 cycles delay 100 4clk 4 clk per2 cycles delay 101 5clk 5 clk per2 cycles delay 110 6clk 6 clk per2 cycles delay 111 7clk 7 clk per2 cycles delay
258 8077b?avr?06/08 atxmega 22.11.6 sdramctrlb - sdra m control register c ? bit 7:6 - wrdly[1:0]: sdram write recovery delay these bits select the write recovery time in number of peripheral 2x clock (clk per2 ) cycles, according to table 22-11 on page 257 . ? bit 5:3 - esrdly[2:0]: sdram exit self refresh to active delay this field defines the delay between cke set high and an activate command in a number of peripheral 2x clock (clk per2 ) cycles, according to table 22-15 on page 258 . ? bit 2:0 - rowcoldly[2:0]: sdram row to column delay this field defines the delay between an activate command and a read/write command as a number of peripheral 2x clock (clk per2 ) cycles, according to table 22-16 on page 258 . bit 7654 3 2 10 +0x09 wrdly[1:0] esrdly[1:0] rowcoldly[1:0] sdramctrlc read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value0000 0 0 00 table 22-14. sdram write recovery delay settings wrdly[1:0] group configuration description 00 0clk 0 clk per2 cycles delay 01 1clk 1 clk per2 cycles delay 10 2clk 2 clk per2 cycles delay 11 3clk 3 clk per2 cycles delay table 22-15. sdram exit self refresh delay settings esrdly[2:0] group configuration description 000 0clk 0 clk per2 cycles delay 001 1clk 1 clk per2 cycles delay 010 2clk 2 clk per2 cycles delay 011 3clk 3 clk per2 cycles delay 100 4clk 4 clk per2 cycles delay 101 5clk 5 clk per2 cycles delay 110 6clk 6 clk per2 cycles delay 111 7clk 7 clk per2 cycles delay table 22-16. sdram row column delay settings rowcoldly[2:0] group co nfiguration description 000 0clk 0 clk per2 cycles delay 001 1clk 1 clk per2 cycles delay 010 2clk 2 clk per2 cycles delay 011 3clk 3 clk per2 cycles delay
259 8077b?avr?06/08 atxmega 22.12 register descripti on - ebi chip select 22.12.1 ctrla - chip select control register a ? bit 7 - res: reserved this bit is reserved and will always be read as zero. ? bit 6:2 - asize[4:0]: chip select address size these bits select the address size for the chip select. this is the size of the block above the base address. 100 4clk 4 clk per2 cycles delay 101 5clk 5 clk per2 cycles delay 110 6clk 6 clk per2 cycles delay 111 7clk 7 clk per2 cycles delay table 22-16. sdram row column delay settings (continued) rowcoldly[2:0] group co nfiguration description bit 7654 3 2 10 +0x00 - asize[4:0] mode[1:0] ctrla read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value0000 0 0 00 table 22-17. address space encoding asize[5:0] group configuration add ress size address lines compared 00000 256b 256 bytes addr[23:8] 00001 512b 512 bytes addr[23:9] 00010 1k 1k bytes addr[23:10] 00011 2k 2k bytes addr[23:11] 00100 4k 4k bytes addr[23:12] 00101 8k 8k bytes addr[23:13] 00110 16k 16k bytes addr[23:14 00111 32k 32k bytes addr[23:15] 01000 64k 64k bytes addr[23:16] 01001 128k 128k bytes addr[23:17] 01010 256k 256k bytes addr[23:18] 01011 512k 512k bytes addr[23:19] 01100 1m 1m bytes addr[23:20] 01101 2m 2m bytes addr[23:21] 01110 4m 4m bytes addr[23:22]
260 8077b?avr?06/08 atxmega ? bit 1:0 - mode[1:0]: chip select mode these bits select the chip select mode and decide what type of interface is used for the external memory or peripheral according to table 22-18 on page 260 . 22.12.2 ctrlb (sram) - chip select control register b this configuration options in this register depend on the chip select mode configuration. the register description below is va lid when the chip select mode is configured for sram or sram lpc. ? bit 7:3 - res: reserved these bits are reserved and will always be read as zero. ? bit 2:0 - srws[2:0]: sram wait state these bits select the number of wait states for sram and sram lpc access as a number of peripheral 2x clock (clk per2 ) cycles, according to table 22-19 on page 260 . 01111 8m 8m bytes addr[23] 10000 16m 16m (1) - other - reserved 1. entire available data space used. table 22-18. chip select mode selection mode[1:0] group configuration description 00 disable chip select disabled 01 sram enable chip select for sram 10 lpc enable chip select for sram lpc 11 sdram enable chip select for sdram (1) 1. sdram can only be selected for cs3 table 22-17. address space encoding (continued) asize[5:0] group configuration add ress size address lines compared bit 7654 3 2 10 +0x01 ---- - srws[2:0] ctrlb read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value0000 0 0 00 table 22-19. wait state selection srws[2:0] group configuration description 000 0clk 0 clk per2 cycles wait state 001 1clk 1 clk per2 cycles wait state 010 2clk 2 clk per2 cycles wait state 011 3clk 3 clk per2 cycles wait state 100 4clk 4 clk per2 cycles wait state
261 8077b?avr?06/08 atxmega 22.12.3 ctrlb (sdram) - chip select control register b this configuration options in this register depend on the chip select mode configuration. the register description below is valid when the chip select mode is configured for sdram . ? bit 7 - sdinitdone: sdram initialization complete this flag is set at the end of the sdram initia lization sequence. the flag will remain set as long as the ebi is enabled and the chip select is configured for sdram. ? bit 6:3 - res: reserved these bits are reserved and will always be read as zero. ? bit 2 - sdsren: sdram self-refresh enable when this bit is written to one the ebi cont roller will send a self-refresh command to the sdram. for leaving the self refresh mode, the bit must be written to zero. ? bit 1:0 sdmode[1:0]: sdram mode these bits select mode when accessing the sdram according to table 22-20 on page 261 . 22.12.4 baseaddr - chip select base address register 101 5clk 5 clk per2 cycles wait state 110 6clk 6 clk per2 cycles wait state 111 7clk 7 clk per2 cycles wait state table 22-19. wait state selection (continued) srws[2:0] group configuration description bit 7 6 5 4 3 2 1 0 +0x01 sdinitdone - - - - sdren sdmode[1:0] ctrlb read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 22-20. sdram mode srmode[1:0] group configuration description 00 normal normal mode. access to the sdram is decoded normally. 01 load load mode. the ebi issues a ?load mode register? command when the sdram is accessed. 10 - reserved 11 - reserved bit 7654 3 2 10 +0x02 baseaddr[15:12] - - - - baseaddrl +0x03 baseaddr[23:16] baseaddrh 15 14 13 12 11 10 9 8 read/write r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value0000 0 0 00 0000 0 0 00
262 8077b?avr?06/08 atxmega ? bit 15:4 - baseaddr[23:12]: chip select base address the base address is the lowest address in the address space enabled by a chip select. together with the chip select address size (asize) setti ng in ?ctrla - chip select control register a? this gives the address space for the chip select. ? bit 3:0 - res: reserved these bits are reserved and will always be read as zero.
263 8077b?avr?06/08 atxmega 22.13 register summary - ebi 22.14 register summar y - ebi chip select address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page +0x00 ctrl sdmode[1:0] lpcmode[1:0] srmode[1:0] ifmode[1:0] +0x01 sdramctrla - - - - sdcas sdrow sdcol[1:0] +0x02 reserved - - - - - - - - +0x03 reserved - - - - - - - - +0x04 refreshl sdram refresh period low byte +0x05 refreshh - - - - - - sdra m refresh period high +0x06 initdlyl sdram initialization time low byte +0x07 initdlyh - - sdram initialization time high byte +0x08 sdramctrlb mrdly[1:0] rowcycdly[[2:0] rpdly[2:0] +0x09 sdramctrlc rwdly[1:0] esrdly[2:0] rowcoldly[2:0] +0x0a reserved - - - - - - - - +0x0b reserved - - - - - - - - +0x0c reserved - - - - - - - - +0x0d reserved - - - - - - - - +0x0e reserved - - - - - - - - +0x0f reserved - - - - - - - - +0x10 cs0 chip select 0 offset address +0x14 cs1 chip select 1 offset address +0x18 cs2 chip select 2 offset address +0x1c cs3 chip select 3 offset address address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page +0x00 ctrla - asize[4:0] mode[1:0] +0x01 ctrlb (sram) - - - - - srws[2:0] (sdram) sdinitdone - - - - sdsren sdmode[1:0] +0x02 baseaddrl chip select base address low byte - - - - +0x03 baseaddrh chip select base address high byte
264 8077b?avr?06/08 xmega a 23. adc - analog to digital converter 23.1 features ? 12-bit resolution ? up to 2 msps conversion rate ? single-ended or diff erential measurements ? signed and un signed mode ? 4 result registers with individual input control ? 8 single-ended inputs ? 8x4 differential inputs without gain ? 8x4 differential input with gain ? 4 internal inputs ? 1x, 2x, 4x, 8x, 16x, 32x or 64x gain ? 4 inputs can be sampled within 1.5 s ? 8-, or 12-bit selectable resolution ? minimum single result propagation delay of 2.5s (8-bit resolution) ? minimum single result propagation delay of 3.5s (12-bit resolution) ? built-in reference ? optional external reference ? optional event triggered co nversion for accurate timing ? optional dma transfer of conversion results ? optional interrupt/even t on compare result 23.2 overview the adc converts analog voltages to digital values. the adc has 12-bit resolution and is capa- ble of converting up to 2 millio n samples per second. the input selection is flexible, and both single-ended and differential measurements can be done. for differential measurements an optional gain stage is available to increase the dynamic range. in addition several internal signal inputs are available. the adc can provide both signed and unsigned results. this is a successive approximation result (sar) adc. a sar adc measures one bit of the conversion result at a time. the xmega adc has a pipeline architecture. this means that a new analog voltage can be sampled and a new adc measurement started while other adc measurements are ongoing. adc measurements can either be started by application software or an incoming event from another peripheral in the device. four different result registers with individual input selection (mux selection) are provided to make it easier for the application to keep track of the data. each result register and mux selection pair is referred to as an adc channel. it is possible to use dma to move adc results directly to memory or peripherals when conversions are done. both internal and external analog reference volta ges can be used. a very accurate internal 1.0v reference is available, providing a conversi on range 0 - 1.0 v in unsigned single ended mode and -1.0 to 1.0v in signed differential mode.
265 8077b?avr?06/08 xmega a figure 23-1. adc overview 23.3 input sources the input sources for the adc are the analog voltage inputs that the adc can measure and convert. four types of measurements can be selected: ? single ended input ? differential input ? differential input with gain ? internal input the analog input pins are used for single ended and differential input, while the internal inputs are directly available inside the device. in dev ices with two adcs, porta pins can be input to adca and portb pins can be input to adcb. for xmega devices with only one adc but with analog input pins on both porta and portb, both porta and portb analog pins can then be used as input. the mux control registers select which input that is converted and the type of measurements in one operation. the four types of measurements and their corresponding muxes are shown in figure 23-4 on page 267 to figure 23-6 on page 268 . the adc itself is always differential, but for non-differential input the negative input for the adc will be connected to an internal fixed value. adc channel 0 result register channel 1 result register channel 2 result register channel 3 result register pin inputs differential pin inputs 1-64 x internal inputs channel 0 mux selection channel 1 mux selection channel 2 mux selection channel 3 mux selection event triggers configuration reference selection
266 8077b?avr?06/08 xmega a 23.3.1 single ended input for single ended measurements all analog input pi ns can be used as inputs. single ended mea- surements can be done in both signed and unsigned mode. the negative input is connected to internal ground in signed mode. in unsigned mode the negative input has a small negative volt- age to ensure that negative offset can always be measured. figure 23-2. single-ended measurement in signed mode figure 23-3. single ended measurement in unsigned mode 23.3.2 differential input without gain when differential input is sele cted all analog input pins can be se lected as positive input, and analog input pins 0 to 3 can be selected as negative input. the adc must be set in signed mode when differential input is used. adc adc0 adc1 adc2 adc3 adc4 adc5 adc6 adc7 + - adc adc0 adc1 adc2 adc3 adc4 adc5 adc6 adc7 v ? + -
267 8077b?avr?06/08 xmega a figure 23-4. differential measurement without gain 23.3.3 differential input with gain when differential input with gain is selected al l analog input pins can be selected as positive input, and analog input pins 4 to 7 can be selected as negative input. when the gain stage is used, the differential analog input is first sa mpled and amplified by the gain stage before the result is fed into the adc. the adc must be set in signed mode when differential input with gain is used figure 23-5. differential measurement with gain 23.3.4 internal input four analog internal signals can be selected as input and measured by the adc. an internal temperature reference is available. measuring the voltage on this will give an adc result representing the current temperature in the microcontroller. the temperature, t, is given as: adc adc0 adc1 adc2 adc3 adc4 adc5 adc6 adc7 + - adc0 adc1 adc2 adc3 adc adc0 adc1 adc2 adc3 adc4 adc5 adc6 adc7 + adc4 adc5 adc6 adc7 1-64 x -
268 8077b?avr?06/08 xmega a the bandgap voltage is an accurate voltage reference inside the microcontroller that is the source of all other references. the bandgap voltage can be measured directly by the adc. v cc can be measured directly, but a divide by 10 is inserted before the adc input. thus, v cc of 1.8 v will be measured as 0.18 v and v cc of 3.6 v will be me asured as 0.36 v. the output from the dac module in the microcontroller can also be measured by the adc. it is the output directly from the dac, and not the sample and hold (s/h) outputs, that is available for the adc. some of the internal signals need to be turned on specifically before they can be used mea- sured. refer to the manual for these modules for details of how to turn them on. when measuring the internal signals, the negat ive input is connected to internal ground in signed mode. in unsigned mode the measurement the negative input has a small negative offset. figure 23-6. internal measurements in signed mode figure 23-7. internal measurements in unsigned mode 23.4 adc channels to facilitate the use of the adc, the design implement s four separate mux c ontrol registers with corresponding result registers. the mux/result register pair is called an adc channel, and this is shown in figure 23-1 on page 265 . each adc channel can be set up individually to measure different input sources, use different start conv ersion triggers, and they use different events and interrupts. the result is stored in different result registers. as an example of the adc channel scheme, one of the mux/result register pairs can be setup to do single-ended measurements triggered by event signal input, the second mux/result pair can t tbd adcresult tbd + ? = adc temp ref dac vcc scaled bandgap ref + - adc tempref dac vcc scaled bandgap v ? + -
269 8077b?avr?06/08 xmega a measure a differential input on another event signal input, and the two last mux/result pairs can measure two other input sources started by the application software. all the adc channels use the same adc for the c onversions, but due to the pipelined design a new conversion can be started on each adc clock cycle. this means that multiple adc conver- sions can be progressing simultaneously and i ndependently without changing the mux settings. a conversion result can be kept in one result register, independently of other result registers that are continuously updated with new conversion results. this can help reduce software complex- ity, and different software modules can start conversions and read conversion results fully independent of each other. 23.5 analog reference the following sources are available as the analog reference (aref) for the adc: ? accurate 1.0v internal voltage reference. ? internal v cc /1.6v voltage. ? external positive reference ap plied to vref pin on porta. ? external positive reference ap plied to vref pin on portb. figure 23-8. analog reference selection 23.6 conversion result the adc can be set up to be either in signed or in unsigned mode. this setting is global for the adc and all adc channels. in signed mode, both negative and positive voltages can be mea- sured, both for single ended and differential input. with 12-bit resolution, the top value of a signed result is 2048 and the re sults will be in the range -2048 to +2047 (0xf800 - 0x07ff). for an unsigned result the top value is 4096 and results will be in the range 0 - 40 95 (0 - 0x0fff). if differential measurements is used in any if the adc channels, the adc must be set in signed mode. in unsigned mode, the negative input to the adc is set to a fixed internal ground and then only single ended or internal signals can be measured. the result of the analog to digital conversion is written to one of the result registers, res. the adc transfer function can be written as: vinp and vinn are the positive and negative inpu t to the adc. gain is always 1 unless differ- ential channels with gain is used. using differential channels with gain 1x, 2x, 4x, 8x, 16x, 32x and 64x is available. the gain should not be changed during an adc conversion. internal ref arefb arefa vcc/1.6v aref res vinp - vinn aref --------------------------------- gain top ?? =
270 8077b?avr?06/08 xmega a the application software selects if an 8- or 12-bit result should be generated. a result with lower resolution will be ava ilable faster. see the ?adc clock and conversion timing? on page 270 for a description on how to calculate the propagation delay. the result registers are 16-bit. an 8-bit result is always represented right adjusted in the 16-bit result registers. right adjusted means that the 8 lsb is found in the low byte. a 12-bit result can be represented both left- or right adjusted. left adjusted means that the 8 msb are found in the high byte. when the adc is in signed mode, the msb repres ents the sign bit. in 12-bit right adjusted mode, the sign bit (bit 11) is padded to bits 12-15 to create a signed 16-bit number directly. in 8-bit mode, the sign bit (bit 7) is padded to the entire high byte. 23.7 starting a conversion before a conversion is started, the desired in put source must be selected for one or more adc channels. an adc conversion for a adc channel can either be started by the application soft- ware writing to the start conversion bit for the adc channel, or from any of the events in the event system. it is possible to write the start conversion bit for several adc channels at the same time, or to use one event to trigger conversions on several adc channels at the same time. 23.8 adc clock and conversion timing the adc is clocked from the peripheral clock . the adc can prescale the peripheral clock to provide an adc clock (clk adc ) that is within the minimum and maximum frequency for the adc. figure 23-9. adc prescaler the maximum adc sample rate is given by the he adc clock frequency (f adc ). the adc can sample a new measurement on every adc clock cycles. 9-bit adc prescaler clk adc prescaler[2:0] clk/4 clk/8 clk/16 clk/32 clk/64 clk/128 clk per clk/256 clk/512 sample rate f adc =
271 8077b?avr?06/08 xmega a the propagation delay of an adc measurement is given by: res is the resolution, 8- or 12-bit. the pr opagation delay will increase by one extra adc clock cycle if gain is used. even though the propagation delay is longer than one adc clock cycle, the pipelined design removes any limitations on sample speed versus propagation delay. 23.8.1 single conversion without gain figure 23-10 on page 271 shows the adc timing for a single conversion without gain. the writ- ing of the start conversion bit, or the event triggering the conversion (start), must occur minimum one peripheral clock cycles before the adc clock cycle where the conversion actually start (indicated with the grey slope of the start trigger). the analog input source is sampled in the first half of the first cycle, and the sample time is always a half adc clock period. the most significant bit (msb) of the result is converted fi rst, and the rest of the bits are converted during the next 3 (for 8-bit results) or 5 (for 12-bit results) cycles. converting one bit takes a half adc clock period. during the last cycle the result is prepared before the interrupt flag is set. the result is available in the result register for readout. figure 23-10. adc timing for one single conversion without gain 23.8.2 single conversion with gain figure 23-11 on page 272 shows the adc timing for one single conversion with gain. as seen in the ?overview? on page 264 the gain stage is placed prior to the actual adc. this means that the gainstage will sample and amp lify the analog input source before the adc samples an con- verts the amplified analog value. compared to a single conversion without gain this adds one adc clock cycle (between start and adc sample) for the gain stage sample and amplify. the sample time for the gain stage is a half adc clock cycle. propagation delay = 1 res 2 ---------- - gain ++ f adc ------------------------------------------ clk adc start adc sample if converting bit 10 9 8 7 6 5 4 3 2 1 lsb 12345678 msb
272 8077b?avr?06/08 xmega a figure 23-11. adc timing for one single conversion with gain 23.8.3 single conversions on two adc channels figure 23-12 on page 272 shows the adc timing for single conversions on two adc channels. the pipelined design enables the second conversion to start on the next adc clock cycle after t the first conversion is started. in this example bo th conversions is triggered at the same time, but for adc channel 1 (ch1) the actual start is not until the adc sample and conversion of the msb for adc channel 0 (ch0) is done. figure 23-12. adc timing for single conversions on two adc channels 23.8.4 single conversions on two adc channels, ch0 with gain figure 23-13 on page 273 shows the conversion timing for single conversions on two adc chan- nels where adc channel 0 uses the gain stage. as the gain stage introduce one addition cycle for the gain sample and amplify, the sample for adc channel 1 is also delayed one adc clock cycle, until the adc sample and msb conversion is done for adc channel 0. adc sample converting bit start if gainstage sample gainstage amplify msb 10 9 8 7 6 5 4 3 2 1 lsb clk adc 12345678 9 clk adc start ch1 adc sample if ch1 start ch0 if ch0 converting bit ch0 converting bit ch1 msb 10 9 8 7 6 5 4 3 2 1 lsb 12345678 9 msb 10 9 8 7 6 5 4 3 2 1 lsb
273 8077b?avr?06/08 xmega a figure 23-13. adc timing for single conversion on two adc channels, ch0 with gain 23.8.5 single conversions on two adc channels, ch1 with gain figure 23-14 on page 273 shows the conversion timing for single conversions on two adc chan- nels where adc channel 1 uses the gain stage. figure 23-14. adc timing for single conversion on two adc channels, ch1 with gain 23.8.6 free running mode on two adc channels with gain figure 23-15 on page 274 shows the conversion timing for all four adc channels in free running mode, ch0 and ch1 without gain and ch2 and ch3 with gain. when set up in free running mode a adc channel will continuously sample and do new conversion s. in this example all adc channels are triggered at the same time, and each adc channel sample and start converting as soon as the previous adc channel is done with it sample and msb conversion. after four adc clock cycles all adc channels have done the firs t sample and started th e first conversion, and each adc channels can then do the sample conversion start for the second conversions. after 8 (for 12-bit mode) adc clock cy cles the first conversion is done for adc channel 0, and the results for the rest of the adc channels is availa ble in the next adc clock cycles. after the next start ch1, wo/gain adc sample if ch1 start ch0, w/gain if ch0 gainstage sample gainstage amplify converting bit ch0 converting bit ch1 msb 10 9 8 7 6 5 4 3 2 1 lsb msb 10 9 8 7 6 5 4 3 2 1 lsb clk adc 12345678 9 10 start ch1, w/gain adc sample if ch1 converting bit ch0 start ch0, wo/gain if ch0 converting bit ch1 gainstage sample gainstage amplify clk adc 12345678 9 10 msb 10 9 8 7 6 5 4 3 2 1 lsb msb 10 9 8 7 6 5 4 3 2 1 lsb
274 8077b?avr?06/08 xmega a clock cycle (in cycle 10) the result from the second adc channel is done and available and so on. in this mode up to 8 conversions are ongoing at the same time. figure 23-15. adc timing for free running mode 23.9 dma transfer the dma controller can be used to transfer adc conversion results to memory or peripherals. a new conversion completed in any of the adc result registers may trigger a dma transfer request. see the dma controller manual for more details on dma transfers. 23.10 interrupts and events the adc can generate both interrupt requests and events. the adc channels have individual interrupt and event settings. interrupt requests and events can be generated either when an adc conversion is complete or if an adc measurement is above or below the adc compare register values. the adc compare register is a 12-bit register that holds a value representing an analog thresh- old voltage. all four adc result registers (adc channels) share the same adc compare register. 23.11 calibration the adc has a built-in calibration mechanism that removes gain error from the conversion result. the adc will be calibrated during production testing, and the calibration value must be loaded from the signature row and into the adc calibration register from software. 23.12 channel priority since the system clock may be faster than the adc clock, it is possible to have the start conver- sion bit set for several adc channels within the same adc clock period. events may also trigger start ch1, wo/gain adc sample start ch0, wo/gain gainstage sample gainstage amplify start ch1, w/gain start ch0, w/gain conv complete 0 1 clk adc 12345678 9 10 2 3 2 3 2 3 2 3 0 1 2 3 0 1 2 3 0
275 8077b?avr?06/08 xmega a conversions on several adc channels and give the same scenario. in this case the adc chan- nel with the lowest number will be prioriti zed. this is shown the timing diagrams in ?adc clock and conversion timing? on page 270 . 23.13 synchronous sampling starting an adc conversion may cause an unknown delay between the software start or event and the actual conversion start since conversion of other higher priority adc channels may be started (or pending), or since the system clock may be much faster than the adc clock. to start an adc conversion immediately on an incoming event, it is possible to flush the adc for all measurements, reset the adc clock and start the co nversion at the next peripheral clock cycle, which then will also be the next adc clock cycle. if this is done all ongoing conversions in the adc pipeline will be lost. the adc can either be flushed from software, or the incoming event can be set up to do this automatically. if flushing is used it is important that the time between each conversion start trigger is longer than the propagation delay to ensure that one conversion is finished before the adc pipeline is flushed and the next conversion is started. in microcontrollers with two adc peripherals, it is possible to start two adc samples synchro- nously in the two adcs by using the sa me event channel to trigger both adcs. 23.14 register description - adc 23.14.1 ctrla - adc control register a ? bits 7:6 ? dmasel[1:0]: dma request selection in addition to giving dma transfer request for each adc channel, the adc can be set up to give a combined request for all channels. the combin ed request is decided according to the dma- sel bits. see table 23-1 for details. ? bits 5:2 ? ch[3:0]start: adc channel start single conversion setting any of these bits will start a conversion on the corresponding adc channel. setting sev- eral bits at the same time will start a conv ersion sweep on the selected adc channels, starting with the channel with lowest number. these bi ts are cleared by hardware when the conversion has started. bit 76543210 +0x00 dmasel[1:0] ch[3:0]start flush enable ctrla read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 23-1. adc dma request selection dmasel[1:0] group co nfiguration description 00 off no combined dma request 01 ch01 adc channel 0 or 1 10 ch012 adc channel 0 or 1 or 2 11 ch0123 adc channel 0 or 1 or 2 or 3
276 8077b?avr?06/08 xmega a ? bit 1 ? flush: adc pipeline flush: writing this bit to one will fl ush the adc pipeline. when this is done the adc clock will be restarted on the next peripheral clock edge and all conversions in progress are aborted and lost. after the flush and the adc clock restart, the adc will resume where it left off. i.e. if a channel sweep was in progress or any conversions was pending, the remaining channel conversions will enter the adc pipeline and complete. ? bit 0 ? enable: adc enable setting this bit enables the adc. 23.14.2 ctrlb - adc control register b ? bits 7:5 - res: reserved these bits are unus ed and reserved for future use. for compatibility with futu re devices, always write these bits to zero when this register is written. ? bit 4 - convmode: adc conversion mode this bit controls whether the adc should work in signed or unsigned mode. for signed opera- tion, this bit must be set to one. if the adc is configured for unsigned mode, only single ended or internal signals can be converted. ? bit 3 - freerun: adc free running mode this bit controls the free running mode for the adc. when the bit is set to one the adc channels defined in the evctrl register are swept repeatedly. ? bits 2:1 - resolution[1:0]: adc conversion result resolution these bits define whether the adc completes the conversion at 12- or 8-bit result. they also define whether the 12-bit result is left or right oriented in the 16-bit result registers. see table 23-2 on page 276 for possible settings. ? bit 0 - res: reserved this bit is unused and reserved fo r future use. for comp atibility with future devices, always write this bit to zero when this register is written. bit 765 4 3 2 1 0 +0x01 - - - convmode freerun resolution[1:0] - ctrlb read/write r r r r/w r/w r/w r/w r initial value 0 0 0 0 0 0 0 0 table 23-2. adc conversion result resolution resolution[1:0] group co nfiguration description 00 12bit 12-bit result, right adjusted 01 reserved 10 8bit 8-bit result, right adjusted 11 left12bit 12-bit result, left adjusted
277 8077b?avr?06/08 xmega a 23.14.3 refctrl - adc reference control register ? bit 7:6 ? res: reserved these bits are unus ed and reserved for future use. for compatibility with futu re devices, always write these bits to zero when this register is written. ? bits 6:4 ? refsel[1:0]: adc reference selection these bits selects the reference and conversion range for the adc according to table 23-3 on page 277 . notes: 1. only available if aref exist on port a. 2. only available it aref exist on port b. ? bit 3:2 ? res: reserved these bits are unus ed and reserved for future use. for compatibility with futu re devices, always write these bits to zero when this register is written. ? bit 1 ? bandgap: bandgap enable setting this bit enables the bandgap to prepare for adc measurement. note that if any other functions are using the bandgap already, this bit do es not need to be set. this could be when the internal 1v reference is used in adc or dac, or if the brown-out detector is enabled. ? bit 0 ? tempref: temperature reference enable setting this bit enables the temperature reference to prepare for adc measurement. 23.14.4 evctrl - adc event control register bit 765432 1 0 +0x02 - - refsel[1:0] - - bandg ap tempref refctrl read/write r r r/w r/w r r r/w r/w initial value 0 0 0 0 0 0 0 0 table 23-3. adc reference configuration refsel[1:0] group configuration description 00 int1v internal 1.0v 01 intvcc internal v cc /1.6 10 (1) arefa external reference from aref pin on port a. 11 (2) arefb external reference fr om aref pin on port b. bit 76543210 +0x03 sweep[1:0] evsel[2:0] evact[2:0] evctrl read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000
278 8077b?avr?06/08 xmega a ? bits 7:6 - sweep[1:0] : adc channel sweep these bits control which adc channels are included in a channel sweep triggered by the event system or in free running mode. see table 23-4 on page 278 . ? bits 5:3 - evsel[2:0]: ev ent channel input select these bits define which event channel should tr igger which adc channel. each setting defines a group of event channels, where the event channels with the lo west number will trigger adc channel 0 and the next event channel will trigger adc channel 1 and so on. the number of incoming event in use is de fined by the evact bits. see table 23-5 on page 278 . ? bits 2:0 - evact[2:0]: adc event mode these bits define how many of the selected event channel that are in use, and also some spe- cial event modes as defined in table 23-5 on page 278 . this is for instance a complete channel sweep triggered by a single event, or an event re-synchronized conversion to achieve a very accurate timing for the conversion. table 23-4. adc channel select sweep[1:0] group configur ation active adc channels for channel sweep 00 0 only adc channel 0 01 01 adc channels 0 and 1 10 012 adc channels 0, 1, and 2 11 0123 adc channels 0, 1, 2, and 3 table 23-5. adc event line select evsel[2:0] group configurat ion selected event lines 000 0123 event channel 0, 1, 2, 3 as selected inputs 001 1234 event channel 1, 2, 3, 4 as selected inputs 010 2345 event channel 2, 3, 4, 5 as selected inputs 011 3456 event channel 3, 4, 5, 6 as selected inputs 100 4567 event channel 4, 5, 6, 7 as selected inputs 101 456 event channel 5, 6, 7 as selected inputs (max 3 event inputs in use) 110 67 event channel 6, 7 as selected inputs (max 2 event inputs in use) 111 7 event channel 7 as selected input (max 1 event input in use)
279 8077b?avr?06/08 xmega a 23.14.5 prescaler - adc clock prescaler register ? bits 7:3 - res: reserved these bits are reserved and will always read as zero. for compatibility with future devices, always write these bits to zero when this register is written. ? bits 2:0 - prescaler[2:0]: adc prescaler configuration these bits define the adc clock relative to the peripheral clock, according to table 23-7 on page 280 . table 23-6. adc event mode select evact[2:0] group configuration event input operation mode 000 none no event inputs 001 ch0 event channel wi th the lowest number, defined by evsel triggers conversion on channel 0 010 ch01 event channel with the two lowest numbers, defined by evsel trigger conversion on channel 0 and 1 respectively 011 ch012 event channel with the three lowest numbers, defined by evsel trigger conversion on channel 0, 1 and 2 respectively 100 ch0123 event channel defined by evsel trigger conversion on channel 0, 1, 2 and 3 respectively 101 sweep one sweep of all active adc channels defined by sweep on incoming event channel with the lowest number, defined by evsel 110 syncsweep one sweep of all active adc channels defined by sweep on incoming event channel with the lowest number, defined by evsel. in addition, the conversion will be synchronized on event to ensure a very accurate timing for the conversion. 111 reserved bit 76543 2 1 0 +0x04 - - - - - prescaler[2:0] prescaler read/write r r r r r r/w r/w r/w initial value 0 0 0 0 0 0 0 0
280 8077b?avr?06/08 xmega a 23.14.6 intflags - adc interrupt flag register ? bits 7:4 - res: reserved these bits are reserved and will always read as zero. for compatibility with future devices, always write these bits to zero when this register is written. ? bits 3:0 - ch[3:0]if: interrupt flags these flags are set when the adc conversion is complete for the corresponding adc channel. if an adc channel is configured for compare mode, the corresponding flag will be set if the com- pare condition is met. chnif is automatically cleared when the adc channel n interrupt vector is executed. the flag can also be cleared by writing a one to its bit location. 23.14.7 temp - adc temporary register ? bits 7:0 - temp[7:0]: adc temporary register this register is used when reading 16-bit registers in the adc controller. the high byte of the 16- bit register is stored here when the low byte read by the cpu. this register can also be read and written from the user software. for more details on 16-bit register access refer to section 3.11 ?accessing 16-bits registers? on page 12 . table 23-7. adc prescaler settings prescaler[2:0] group configuration system clock division factor 000 div4 4 001 div8 8 010 div16 16 011 div32 32 100 div64 64 101 div128 128 110 div256 256 111 div512 512 bit 76543210 +0x06 ---- ch[3:0]if intflags read/write r r r r r/w r/w r/w r/w initial value00000000 bit 76543210 +0x07 temp[7:0] temp read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000
281 8077b?avr?06/08 xmega a 23.14.8 cal - adc calibration value registers ? bits 7:0 - cal[7:0]: adc calibration value this is the calibration value to cancel the gain error. the adc is calibrated during production programming, the calibration value must be read from the signature row and written to the cal register from software. 23.14.9 chnresh - adc channe l n result register high the chnresl and chnresh register pair represents the 16-bit value chnres. for details on reading 16-bit register refer to section 3.11 ?accessing 16-bits registers? on page 12 . 23.14.9.1 12-bit mode, left adjusted ? bits 7:0 - chres[11:4]: adc channel result, high byte these are the 8 msb of the 12-bit adc result. 23.14.9.2 12-bit mode, right adjusted ? bits 7:4 - res: reserved these bits will in practice be the extension of the sign bit chres11 when adc works in differen- tial mode and set to zero when adc works in signed mode. ? bits 3:0 - chres[11:8]: adc channel result, high byte these are the 4 msb of the 12-bit adc result. 23.14.9.3 8-bit mode ? bits 7:0 - res: reserved these bits will in practice be the extension of the sign bit chres7 when adc works in signed mode and set to zero when adc works in single-ended mode. 23.14.10 chnresl - adc channe l n result register low bit 76543210 +0x0c cal[7:0] cal read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 12-bit, left chres[11:4] 12-bit, right ---- chres[11:8] 8-bit -------- read/writerrrrrrrr initial value00000000 bit 76543210 12-/8- chres[7:0] 12-bit, left chres[3:0] ---- read/writerrrrrrrr initial value00000000
282 8077b?avr?06/08 xmega a 23.14.10.1 12-/8-bit mode ? bits 7:0 - chres[7:0]: adc channel result, low byte these are the 8 lsb of the adc result. 23.14.10.2 12-bit mode, left adjusted ? bits 7:4 - chres[3:0]: adc channel result, low byte these are the 4 lsb of the 12 bit adc result. ? bits 3:0 - res: reserved these bits are reserved and will always read as zero. for compatibility with future devices, always write these bits to zero when this register is written. 23.14.11 cmph - adc compare register high the cmph and cmpl register pair represents the 16-bit value adc compare (cmp). for details on reading and writing 16-bit registers refer to section 3.11 ?accessing 16-bits registers? on page 12 . ? bits 7:0 - cmp[15:0]: adc compare value high byte these are the 8 msb of the 16-bit adc compare value. n signed mode, the number representa- tion is 2's complement and the msb is the sign bit. 23.14.12 cmpl - adc compare register low ? bits 7:0 - cmp[7:0]: adc compare value high byte these are the 8 lsb of the 16-bit adc compare value. in signed mode, the number representa- tion is 2's complement. 23.15 register descr iption - adc channel 23.15.1 ctrl - adc channel control register bit 76543210 +0x19 cmp[15:0] cmph read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 +0x18 cmp[7:0] cmpl read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 +0x00 start - - gain[2:0} inputmode[1:0] ctrl read/write r/w r r r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0
283 8077b?avr?06/08 xmega a ? bit 7 - start: start conversion on channel writing this to one will start a c onversion on the channe l. the bit is cleared by hardware when the conversion has started. writin g this bit to one when it alread y is set will have no effect. writ- ing or reading these bits is equivalent to writing the ch[3:0]start bits in ?ctrla - adc control register a? on page 275 . ? bits 6:5 - res: reserved these bits are unus ed and reserved for future use. for compatibility with futu re devices, always write these bits to zero when this register is written. ? bits 4:3 - gain[2:0]: adc gain factor these bits define the gain factor in order to amplify input signals before adc conversion. see table 23-6 on page 279 for different gain factor settings. gain is only valid with certain mux settings, see ?muxctrl - adc channel mux control registers? on page 284 . ? bit 1:0 - inputmode[1:0]: channel input mode these bits define the channel mode. this setting is independent of the adc convmode (signed/unsigned mode) setting, but differential input mode can only be done in adc signed mode. in single ended inpu t mode, the negative input to the adc will be connected to a fixed value both for adc signed and unsigned mode. table 23-8. adc gain factor gain[2:0] group configuration gain factor 000 1x 1x 001 2x 2x 010 4x 4x 011 8x 8x 100 16x 16x 101 32x 32x 110 64x 64x 111 reserved table 23-9. channel input modes, convmode=0 (unsigned mode) inputmode[1:0] group configuration description 00 internal internal positive input signal 01 singleended single-ended positive input signal 10 reserved 11 reserved
284 8077b?avr?06/08 xmega a 23.15.2 muxctrl - adc channel mux control registers the mux register defines the input source for the channel. ? bit 7 - res: reserved this bit is unused and reserved fo r future use. for comp atibility with future devices, always write this bit to zero when this register is written. ? bits 6:3 - muxpos[3:0]: mux selection on positive adc input these bits define the mux selection for the positive adc input. table 23-11 on page 284 and table 23-12 on page 285 shows the possible input selection for the different input modes. table 23-11. adc muxpos configuration when inputmode[1:0] = 00 (internal) is used table 23-10. channel input modes, co nvmode=1 (signed mode) inputmode[1:0] group co nfiguration description 00 internal internal positive input signal 01 singleended single-ended positive input signal 10 diff differential input signal 11 diffwgain differential input signal with gain bit 7 6543210 +0x01 - muxpos[3:0] - muxneg[1:0] muxctrl read/write r r/w r/w r/w r/w r r/w r/w initial value 0 0 0 0 0 0 0 0 muxpos[2:0] group configuration analog input 000 temp temperature reference. 001 bandgap bandgap voltage 010 scaledvcc 1/10 scaled v cc 011 dac dac output 100 reserved 101 reserved 110 reserved 111 reserved
285 8077b?avr?06/08 xmega a table 23-12. adc muxpos configuration when inputmode[1:0] = 01 (single-ended), inputmode[1:0] = 10 (differential) or inputpmode[1:0] = 1 (differential with gain) is used. positive input can be selected from another analog port than main on devices with one adc. this is done by setting the muxpos3 bit. ? bits 2 - res: reserved this bit is unused and reserved fo r future use. for comp atibility with future devices, always write this bit to zero when this register is written. ? bits 1:0 - muxneg[1:0]: mux selection on negative adc input these bits define the mux selection for the nega tive adc input when differential measurements are done. for internal or single-ended measurements, these bits are not in use. table 23-13 on page 285 and table 23-14 on page 285 shows the possible input sections. muxpos[2:0] group configuration analog input () 000 pin0 adc0 pin 001 pin1 adc1 pin 010 pin2 adc2 pin 011 pin3 adc3 pin 100 pin4 adc4 pin 101 pin5 adc5 pin 110 pin6 adc6 pin 111 pin7 adc7 pin table 23-13. adc muxneg configuration, inputmode[ 1:0] = 10, differential without gain. muxnex[1:0] group configuration analog input 00 pin0 adc0 pin 01 pin1 adc1 pin 10 pin2 adc2 pin 11 pin3 adc3 pin table 23-14. adc muxneg configuration,inputmode[1:0] = 11, differential with gain. muxneg[1:0] group configuration analog input 00 pin4 adc4 pin 01 pin5 adc5 pin 10 pin6 adc6 pin 11 pin7 adc7 pin
286 8077b?avr?06/08 xmega a ? bit 0 - res: reserved this bit is unused and reserved fo r future use. for comp atibility with future devices, always write this bit to zero when this register is written. 23.15.3 intctrl - adc channel interrupt control registers ? bits 7:4 ? res: reserved these bits are unus ed and reserved for future use. for compatibility with futu re devices, always write these bits to zero when this register is written. ? bit 3:2 ? intmode: adc interrupt mode these bits select the interrupt mode for channel n according to table 23-15 . ? bits 1:0 ? intlvl[1:0]: adc interrupt priority level and enable these bits enable the adc channel interrupt and select the interrupt level as described in ?inter- rupts and programmable multi-level interrupt controller? on page 108 . the enabled interrupt will be triggered when the if in the intflags register is set. 23.15.4 intflag - adc channel interrupt flag registers ? bits 7:1 ? res: reserved these bits are reserved and will always read as zero. for compatibility with future devices, always write these bits to zero when this register is written. ? bit 0 ? if: adc channel interrupt flag the interrupt flag is set when the adc conversion is complete. if the cha nnel is configured for compare mode, the flag will be set if the compar e condition is met. if is automatically cleared when the adc channel interrupt vector is executed. the bit can also be cleared by writing a one to the bit location. bit 76543210 +0x02 - - - - intmode[1:0} intlvl[1:0] intctrl read/write r r r r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 23-15. adc interrupt mode intmode[1:0] group configuration interrupt mode 00 complete conversion complete 01 below compare result below threshold 10 reserved 11 above compare result above threshold bit 76543210 +0x03 - - - - - - - if intflag read/writerrrrrrrr/w initial value 0 0 0 0 0 0 0 0
287 8077b?avr?06/08 xmega a 23.15.5 resh - adc channel n result register high for all result registers and with any adc result resolution, a signed number is represented in 2?s complement form and the msb represents the sign bit. the resl and resh register pair represents the 16-bit value adcresult. reading and writ- ing 16-bit values require special attention, refer to ?accessing 16-bits registers? on page 12 for details. 23.15.5.1 12-bit mode, left adjusted ? bits 7:0 - res[11:4]: adc channel result, high byte these are the 8 msb of the 12-bit adc result. 23.15.5.2 12-bit mode, right adjusted ? bits 7:4 - res: reserved these bits will in practice be the extension of the sign bit chres11 when adc works in differen- tial mode and set to zero when adc works in signed mode. ? bits 3:0 - res[11:8]: adc channel result, high byte these are the 4 msb of the 12-bit adc result. 23.15.5.3 8-bit mode ? bits 7:0 - res: reserved these bits will in practice be the extension of the sign bit chres7 when adc works in signed mode and set to zero when adc works in single-ended mode. 23.15.6 resl - adc channel n result register low 23.15.6.1 12-/8-bit mode ? bits 7:0 - res[7:0]: adc channel result, low byte these are the 8 lsb of the adc result. bit 76543210 12-bit, left. +0x05 res[11:4] 12-bit, right ---- res[11:8] 8-bit -------- read/writerrrrrrrr initial value00000000 bit 76543210 12-/8- +0x04 res[7:0] 12-bit, left. res[3:0] ---- read/writerrrrrrrr initial value00000000
288 8077b?avr?06/08 xmega a 23.15.6.2 12-bit mode, left adjusted ? bits 7:4 - res[3:0]: adc channel result, low byte these are the 4 lsb of the 12 bit adc result. ? bits 3:0 - res: reserved these bits are reserved and will always read as zero. for compatibility with future devices, always write these bits to zero when this register is written.
289 8077b?avr?06/08 xmega a 23.16 register summary this is the i/o summary when the adc is configured to give standard 12-bit results. i/o summary for 8-bit and 12-bit left adjusted will be similar, but with some changes in the result registers chnresh and chnresl. 23.16.1 common registers 23.16.2 channel registers address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page +0x00 ctrla dmasel[1:0] ch[3:0]start flush enable 275 +0x01 ctrlb - - - convmode freerun resolution[1:0] - 276 +0x02 refctrl - - refsel[1 :0] - - bandgap tempref 277 +0x03 evctrl sweep[1:0] evsel[2:0] evact[2:0] 277 +0x04 prescaler - - - - - prescaler[2:0] 279 +0x05 cal cal 281 +0x06 intflags - - - - ch[3:0]if 280 +0x07 temp temp[7:0] 280 +0x08 reserved - - - - - - - - +0x09 reserved - - - - - - - - +0x0a reserved - - - - - - - - +0x0b reserved - - - - - - - - +0x0c reserved - - - - - - - - +0x0d reserved - - - - - - - - +0x0e reserved - - - - - - - - +0x0f reserved - - - - - - - - +0x10 ch0resl ch0res[7:0] 281 +0x11 ch0resh ch0res[15:8] 281 +0x12 ch1resl ch1res[7:0] 281 +0x13 ch1resh ch1res[15:8] 281 +0x14 ch2resl ch2res[7:0] 281 +0x15 ch2resh ch2res[15:8] 281 +0x16 ch3resl ch3res[7:0] 281 +0x17 ch3resh ch3res[15:8] 281 +0x18 cmpl cmp[7:0] 282 +0x19 cmph cmp[15:8] 282 +0x1a reserved - - - - - - - - +0x1b reserved - - - - - - - - +0x1c reserved - - - - - - - - +0x1d reserved - - - - - - - - +0x1e reserved - - - - - - - - +0x1f reserved - - - - - - - - +0x20 ch0 offset +0x28 ch1 offset +0x30 ch2 offset +0x38 ch3 offset address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page +0x00 ctrl start - - gain[2:0] inputmode[1:0] 282 +0x01 muxctrl - muxpos[3:0] - muxneg[3:0] 284 +0x02 intctrl - - - - intmode[1:0] intlvl[1:0] 286 +0x03 intflag - - - - - - - if 286 +0x04 resl res[7:0] 287 +0x05 resh res[15:8] 287 +0x06 reserved - - - - - - - - +0x07 reserved - - - - - - - -
290 8077b?avr?06/08 xmega a 24. dac - digital to analog converter 24.1 features ? 12-bit resolution ? up to 1 msps conversion rate ? flexible conversion range ? multiple trigger sources ? 1 continuous time or 2 sample/hold (s/h) outputs ? built-in offset an d gain calibration ? high drive capabilities ? internal/exter nal reference ? possibility to use as input to analog comparator or adc ? power reduction mode 24.2 overview the dac converts digital values to analog voltages. the dac has 12-bit resolution and is capa- ble of converting 1 million samples per seco nd. the output from the dac can either be continuous to one pin, or fed to two different pins using a sample and hold (s/h) circuitry. a sep- arate low power mode is available, and the dac can be gain and offset calibrated. the output signal swing is defined by the reference voltage aref. the following sources are available as aref in the dac: ?av cc ? internal 1.0v ? external reference applied to the aref pin on porta or portb the output voltage from a dac channel is given as: figure 24-1 on page 291 illustrates the basic functionality rela ted to the dac. not all functional- ity is shown. v dacx chndata 0 xfff --------------------------- - aref ? =
291 8077b?avr?06/08 xmega a figure 24-1. dac overview 24.3 starting a conversion conversions are either done when data is written to the data registers, or timed by an incoming event. if auto trigger mode is not selected, a new conver sion is automatically started when there is a new value in the dac data regist er. when auto trigger mode is selected, the new conversion will be started on an incoming event from the selected event channel if there is new data in the data register which has not been converted. both application software and the dma controller may write to the data registers. 24.4 output channels the output from the dac can either be continuous to one pin (channel 0), or fed into two differ- ent pins using a sample and hold circuitry (s/h). with s/h these two outputs can act independently and create two different analog signals, different in both voltage and frequency. the two s/h outputs have individual data and conversion control registers. the dac output may be used as input to other peripherals in xmega, such as the analog comparator or the analog to digital converter. it is the output directly from the dac, not the s/h outputs, that is available for these peripherals. 24.5 dac clock the dac is clocked from the peripheral clock (clk per ) directly. the dac conversion interval and refresh rate in s/h mode is configured relative to the peripheral clock. 24.6 timing constraints some timing constraints are given to make sure the dac operates correctly. the timing con- straints are relative to the frequency of the peri pheral clock. not meeti ng the timing constraints may reduce the accuracy of dac conversions. ? the dac sampling time is the time interval between a completed channel conversion until starting a new conversion. this should not be le ss than 1 s for single channel mode and 1,5 s for dual channel (s/h) mode. output control and driver dac ch0data ch1data 12 12 12 avcc aref vbg refsel dac ctrl trig enable adc ac dac ch0 dac ch1
292 8077b?avr?06/08 xmega a ? the dac refresh time is the time interval between each time a channel is updated in dual channel mode. this should not be more than 30 s. 24.7 low power mode to reduce the power consumpti on in dac conversions, the dac may be set in a low power mode. in low power mode, the dac is turned off between each conversion. conversion time will be longer if new conversion s are started in this mode. 24.8 calibration to achieve optimal accuracy, it is possible to calibrate both gain and offset error in the dac. there is a 7-bit calibration value for gain adjustment and a 7-bit calibration value for offset adjustment. to get the best calibration result it is recommended to use the same aref, output channel selection, sampling time, and refresh interval when calibrating as in normal dac operation. the theoretical transfer function for the dac was shown in ?overview? on page 290 . including errors, the adc output value can be expressed as: in an ideal dac, gain is 1 and offset is 0. 24.9 register description 24.9.1 ctrla ? dac co ntrol register a ? bits 7:5 - res: reserved these bits are unus ed and reserved for future use. for compatibility with futu re devices, always write these bits to zero when this register is written. ? bit 4 - idoen: dac internal output enable setting this bit routs the internal dac output to the adc and analog comparator muxes. ? bit 3 - ch1en: dac channel 1 output enable setting this bit will make channel 1 available on pin while clearing the bit makes channel 1 only available for internal use. ? bit 2 - ch0en: dac channel 0 output enable setting this bit will make channel 0 available on pin while clearing the bit makes channel 0 only available for internal use. v dacxx gain chndata 0 xfff --------------------------- - offset + ? = bit 76543210 +0x00 - - - idoen ch1en ch0en . enable ctrla read/write r r r r/w r r/w r/w r/w initial value00000000
293 8077b?avr?06/08 xmega a ? bit 1 - res - reserved this bit is unused and reserved fo r future use. for comp atibility with future devices, always write this bit to zero when this register is written. ? bit 0 - enable: dac enable this bit enables the entire dac. 24.9.2 ctrlb ? dac co ntrol register b ? bit 7 - res: reserved this bit is unused and reserved fo r future use. for comp atibility with future devices, always write this bit to zero when this register is written. ? bits 6:5 - chsel[1:0]: dac channel selection these bits control wether the dac should operate with single or dual channel outputs. table 24- 1 shows the available selections. ? bits 4:2 - res: reserved these bits are unus ed and reserved for future use. for compatibility with futu re devices, always write these bits to zero when this register is written. ? bit 1 - ch1trig: dac auto trigged mode channel 1 if this bit is set, the incoming event on the event channel selected in the evctrl register will start the conversion when a new value is written to high byte of the data register ch1data. ? bit 0 - ch0trig: dac auto trigged mode channel 0 if this bit is set, the incoming event on the event channel selected in the evctrl register will start the conversion when a new value is written to high byte of the data register ch0data. 24.9.3 ctrlc ? dac co ntrol register c bit 76543210 +0x01 - chsel[1:0] - - - ch1trig ch0trig ctrlb read/write r r/w r r r r r/w r/w initial value00000000 table 24-1. dac channel selection chsel[1:0] description 00 single channel operation (for channel 0 only) 01 reserved 10 duel channel operation (s/h for channel 0 and channel 1) 11 reserved bit 76543210 +0x02 - - - refsel[1:0] - - leftadj ctrlc read/write r r r r/w r/w r/w r/w r/w initial value00000000
294 8077b?avr?06/08 xmega a ? bits 7:5 - res: reserved these bits are unus ed and reserved for future use. for compatibility with futu re devices, always write these bits to zero when this register is written. ? bits 4:3 - refsel[1:0]: dac reference selection these bits control the reference and thus the conversion range of the dac. table 24-2 shows the available options. ? bit 2:1 - res: reserved these bits are unus ed and reserved for future use. for compatibility with futu re devices, always write these bits to zero when this register is written. ? bit 0 - leftadj: dac left-adjust value if this bit is set, ch0data and ch1data are left-adjusted. 24.9.4 evctrl ? dac event control register ? bits 7:3 - res: reserved these bits are unus ed and reserved for future use. for compatibility with futu re devices, always write these bits to zero when this register is written. ? bits 2:1 - evsel[2:0]: dac e vent channel input selection these bits define which channel from the event system that is used for triggering a dac conversion. table 24-3 shows the available selections. table 24-2. dac reference selection refsel[1:0] group configuration description 00 int1v internal 1.0 v 01 avcc av cc 10 arefa aref on porta 11 arefb aref on portb bit 76543210 +0x03 ----- evsel[2:0] evctrl read/writerrrrrr/wr/wr/w initial value 0 0 0 0 0 0 0 0
295 8077b?avr?06/08 xmega a 24.9.5 timctrl ? dac timing control register ? bit 7 - res: reserved this bit is unused and reserved fo r future use. for comp atibility with future devices, always write this bit to zero when this register is written. ? bits 6:4 - [2:0]: - conintval - dac conversion interval these bits control the minimum interval between two successive conversions. the interval must be set relative to the peripheral clock (clk per ) to ensure that a new conversion is not started until the result from the previous conversion has se ttled. the dac conversion interval should never be set lower than 1 s during single channel operation, and not lower than 1,5 s during dual channel (s/h) operation. table 24-4 shows the available control settings as a number of periph- eral clock cycles. to allow for longer conversion intervals during dual channel operation, a 50% increase in the number peripheral clock cycles is automatically added. table 24-3. dac event input selection evsel[2:0] group config uration description 000 0 event channel 0 as input to dac 001 1 event channel 1 as input to dac 010 2 event channel 2 as input to dac 011 3 event channel 3 as input to dac 100 4 event channel 4 as input to dac 101 5 event channel 5 as input to dac 110 6 event channel 6 as input to dac 111 7 event channel 7 as input to dac bit 76543210 +0x04 - conintval[2:0] refresh[3:0] timctrl read/write r r/w r/w r/w r/w r/w r/w r/w initial value00000000 table 24-4. dac conversion interval conintcal[2:0] group configuration clk per cycles for single channel operation clk per cycles for dual channel (s/h) operation 000 1clk 1 clk 1 clk 001 2clk 2 clk 3 clk 010 4clk 4 clk 6 clk 011 8clk 8 clk 12 clk 100 16clk 16 clk 24 clk 101 32clk 32 clk 48 clk 110 64clk 64 clk 96 clk 111 128clk 128 clk 192 clk
296 8077b?avr?06/08 xmega a the number of clock cycles selected multiplied wit h the period of the peripheral clock gives the minimum dac conversion internal. ? bits 3:0 - refresh[3:0]: dac channel refresh timing control these bits control time interval between each time a channel is refreshed in dual channel (s/h) mode. the interval must be set relative to the pe ripheral clock to avoid loosing accuracy of the converted value. table 24-5 shows the available timing control settings as a number of periph- eral clock cycles. the number of clock cycles selected multiplied wit h the period of the peripheral clock gives the dac refresh time. 24.9.6 status ? dac status register ? bits 7:2 - res: reserved these bits are unus ed and reserved for future use. for compatibility with futu re devices, always write these bits to zero when this register is written. table 24-5. dac channel refresh control selection refresh[3:0] group configuration clk per cycles refresh interval 0000 16clk 16 clk 0001 32clk 32 clk 0010 64clk 64 clk 0011 128clk 128 clk 0100 256clk 256 clk 0101 512clk 512 clk 0110 1024clk 1024 clk 0111 2048clk 2048 clk 1000 4096clk 4096 clk 1001 8192clk 8192 clk 1010 16384clk 16384 clk 1011 32768clk 32768 clk 1100 65536clk 65536 clk 1101 reserved 1110 reserved 1111 off auto refresh off bit 76543210 +0x05 ------ch1drech0drestatus read/writerrrrrrr/wr/w initial value 0 0 0 0 0 0 0 0
297 8077b?avr?06/08 xmega a ? bit 1 - ch1dre: dac channel 1 data register empty this bit indicates that the data register for channel 1 is empty, meaning that a new conversion value may be written. if the bit is cleared, writing to the data register may cause losing a conver- sion value. this bit is directly used for dma request. ? bit 0 - ch0dre: dac channel 0 data register empty this bit indicates that the data register for channel 0 is empty, meaning that a new conversion value may be written. if the bit is cleared, writing to the data register may cause losing a conver- sion value.this bit is directly used for dma request. 24.9.7 ch0datah ? dac channel 0 data register high the two registers chndatah and chndatal are the high byte and low byte respectively of the 12-bit value chndata that is converted to an analog voltage on dac channel n. by default, the 12 bits are distributed with 8 bits in chndat al and 4 bits in 4 lsb position of chndatah (right-adjusted).to select left-adjusted data it is possible by setting the leftadj bit in the ctrlc register. when this is selected, it is also possible to do 8-bit conversions by writing only chndatah register. 24.9.7.1 right-adjusted ? bits 7:4 - res: reserved these bits are unus ed and reserved for future use. for compatibility with futu re devices, always write these bits to zero when this register is written. ? bits 3:0 - chdata[11:8]: dac conversion data register channel 0, 4 msb these bits are the 4 msb of the 12-bit value to convert to channel 0 in right-adjusted mode. 24.9.7.2 left-adjusted ? bits 7:0 - chdata[11:4]: dac conversion data register channel 0, 8 msb these bits are the 8 msb of the 12-bit value to convert to channel 0 in left-adjusted mode. bit 76543210 right-adjust +0x19 - - - - chdata[11:8] left-adjust chdata[11:4] right-adjust read/write r r r r r/w r/w r/w r/w left-adjust read/write r/w r/w r/w r/w r/w r/w r/w r/w right-adjustinitial value 00000000 left-adjustinitial value 00000000
298 8077b?avr?06/08 xmega a 24.9.8 ch0datal ? dac channel 0 data register low 24.9.8.1 right-adjusted ? bits 7:0 - chdata[7:0]: dac conversion data register channel 0, 8 lsb these bits are the 8 lsb of the 12-bit value to convert to channel 0 in right-adjusted mode. 24.9.8.2 left-adjusted ? bits 7:4 - chdata[3:0]: dac conversion data register channel 0, 4 lsb these bits are the 4 lsb of the 12-bit value to convert to channel 0 in left-adjusted mode. ? bits 3:0 - res: reserved these bits are unus ed and reserved for future use. for compatibility with futu re devices, always write these bits to zero when this register is written. 24.9.9 ch1datah ? dac channel 1 data register high 24.9.9.1 right-adjusted ? bits 7:4 - res: reserved these bits are unus ed and reserved for future use. for compatibility with futu re devices, always write these bits to zero when this register is written. ? bits 3:0 - chdata[11:8]: dac conversion data register channel 1, 4 msb these bits are the 4 msb of the 12-bit value to convert to channel 1 in right-adjusted mode. 24.9.9.2 left-adjusted ? bits 7:0 - chdata[11:4]: dac conversion data register channel 1, 8 msb these bits are the 8 msb of the 12-bit value to convert to channel 1 in left-adjusted mode. bit 76543210 right-adjust +0x18 chdata[7:0] left-adjust chdata[3:0] ---- right-adjust read/write r/w r/w r/w r/w r/w r/w r/w r/w left-adjust read/write r/w r/w r/w r/w r r r r right-adjustinitial value 00000000 left-adjustinitial value 00000000 bit 76543210 right-adjust +0x1b - - - - chdata[11:8] left-adjust chdata[11:4] right-adjust read/write r r r r r/w r/w r/w r/w left-adjust read/write r/w r/w r/w r/w r/w r/w r/w r/w right-adjustinitial value 00000000 left-adjustinitial value 00000000
299 8077b?avr?06/08 xmega a 24.9.10 ch1datal ? dac channel 1 data register low byte 24.9.10.1 right-adjusted ? bits 7:0 - chdata[7:0]: dbc conversi on data register channel 1, 8 lsb these bits are the 8 lsb of the 12-bit value to convert to channel 1 in right-adjusted mode. 24.9.10.2 left-adjusted ? bits 7:4 - chdata[3:0]: dac conversion data register channel 1, 4 lsb these bits are the 4 lsb of the 12-bit value to convert to channel 1 in left-adjusted mode. ? bits 3:0 - res: reserved these bits are unus ed and reserved for future use. for compatibility with futu re devices, always write these bits to zero when this register is written. 24.9.11 gaincal ? dac gain calibration register ? bit 7 - res: reserved this bit is unused and reserved fo r future use. for comp atibility with future devices, always write this bit to zero when this register is written. ? bits 6:0 - gaincal[6:0]: dac gain calibration value these bits are used to compensate the gain error in the dac. see ?calibration? on page 292 for details on how to calibrate gain. 24.9.12 offsetcal ? dac offset calibration register ? bit 7 - res: reserved this bit is unused and reserved fo r future use. for comp atibility with future devices, always write this bit to zero when this register is written. bit 76543210 right-adjust +0x1a chdata[7:0] left-adjust chdata[3:0] - - - - right-adjust read/write r/w r/w r/w r/w r/w r/w r/w r/w left-adjust read/write r/w r/w r/w r/w r r r r right-adjust initial value 0 0 0 0 0 0 0 0 left-adjust initial value 0 0 0 0 0 0 0 0 bit 76543210 +0x08 - gaincal[6:0] gaincal read/write r r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 +0x09 - offsetcal[6:0] offsetcal read/write r r/w r/w r/w r/w r/w r/w r/w initial value00000000
300 8077b?avr?06/08 xmega a ? bits 6:0 - offsetcal[6:0]: dac offset calibration value these bits are used to compensate the offset error in the dac. see ?calibration? on page 292 for details on how to calibrate offset.
301 8077b?avr?06/08 xmega a 24.10 register summary this is the i/o summary when the dac is configured to give standard 12-bit results. i/o sum- mary for 12-bit left adjusted will be similar, but with some changes in the data registers chndatal and chndatah. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page +0x00 ctrla - - - - ch1en ch0en lpmode enable 292 +0x01 ctrlb - chsel[1:0] - - - ch1trig ch0trig 293 +0x02 ctrlc - - - refsel[1:0] - - leftadj 293 +0x03 evctrl - - - - - evsel[2:0] 294 +0x04 timctrl - conintval[2:0] refresh[3:0] 295 +0x05 status - - - - - - ch1dre ch0dre 296 +0x06 reserved - - - - - - - - +0x07 reserved - - - - - - - - +0x08 gaincal - gaincal[6:0] 299 +0x09 offsetcal - offsetcal[6:0] 299 +0x10 reserved - - - - - - - - +0x11 reserved - - - - - - - - +0x12 reserved - - - - - - - - +0x13 reserved - - - - - - - - +0x14 reserved - - - - - - - - +0x15 reserved - - - - - - - - +0x16 reserved - - - - - - - - +0x17 reserved - - - - - - - - +0x18 ch0datal chdata[7:0] 298 +0x19 ch0datah - - - - chdata[11:8] 297 +0x1a ch1datal chdata[7:0] 299 +0x1b ch1datah - - - - chdata[11:8] 298
302 8077b?avr?06/08 xmega a 25. ac - analog comparator 25.1 features ? flexible input selection ? high speed option ? low power option ? selectable input hysteresis ? analog comparator output available on pin ? window mode 25.2 overview the analog comparator (ac) compares the voltage level on two inputs and gives a digital output based on this comparison. the analog comparator may be configured to give interrupt requests and/or events upon several different combinations of input change. two important properties of the analog comparator when it comes to the dynamic behavior, are hysteresis and propagation delay. both these parameters may be adjusted in order to find the optimal operation for each application. the analog comparators are always grouped in pairs (ac0 and ac1) on each analog port. they have identical behavior but separate control registers.
303 8077b?avr?06/08 xmega a figure 25-1. analog comparator overview. ac0 + - pin inputs internal inputs pin inputs internal inputs vcc scaled interrupt sensitivity control interrupts ac1 + - pin inputs internal inputs pin inputs internal inputs vcc scaled events pin 0 output
304 8077b?avr?06/08 xmega a 25.3 input channels each analog comparator has one positive and one negative input. each input may be chosen among a wide selection of input channels: the analog input pins, internal inputs and a scaled inputs. the digital output from the analog comparator is one when the difference between the positive and the negative input is positive, and zero when the difference is negative. 25.3.1 pin inputs the analog input pins on the port can be selected as input to the analog comparator. 25.3.2 internal inputs there are three internal inputs that are directly available for the analog comparator: ? output from the dac (if available on the specific device). ? bandgap reference voltage. ? voltage scaler that can do a 64-level scaling of the internal vcc voltage. 25.4 start of signal compare in order to start a signal compare, the analog comparator must be configured with the preferred properties and inputs, before the module is enabled to start comparing the two selected inputs. the result of the comparison is continuous and available for application software and the event system. 25.5 generating inte rrupts and events the analog comparator can be configured to generate interrupts when the output toggles, when output changes from zero to one (rising edge) or when the output changes from one to zero (fall- ing edge). events will be generated for th e same condition as the in terrupt, and at all times, regardless of the interrupt being enabled or not. 25.6 window mode two analog comparators on the same analog port can be configured to work together in win- dow mode. in this mode a voltage range may be defined, and the analog comparators may give information about whether an input signal is within this range or not.
305 8077b?avr?06/08 xmega a figure 25-2. analog comparator window mode 25.7 input hysteresis application software can select between no, low, and high hysteresis. adding hysteresis can avoid constant toggling of the output if the i nput signals are very close to each other and some noise exists in either of the signals or in the system. 25.8 power consumption vs. propagation delay it is possible to enable high-speed mode to get the shortest possible propagation delay. this mode consumes more power than the default low-power mode that has a longer propagation delay. 25.9 register description 25.9.1 acnctrl ? analog comparator n control register ? bits 7:6 - intmode[1:0]:analog comparator interrupt modes these bits configure the interrupt mode for analog comparator n according to table 25-1 . ac0 + - ac1 + - input signal upper limit of window lower limit of window interrupt sensitivity control interrupts events bit 7654 3210 +0x00 / +0x01 intmode[1:0] intlvl[1:0] hsmode hysmode[2:0] enable acnctrl read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 25-1. analog comparator n interrupt settings intmode[1:0] group configuration description 00 bothedges comparator interrupt on output toggle 01 - reserved 10 falling comparator interrupt or event on falling output edge 11 rising comparator interrupt or event on rising output edge
306 8077b?avr?06/08 xmega a ? bits 5:4 - intlvl[1:0]: analog comparator interrupt level these bits enable the analog comparator n interrupt and select the interrupt level as described in section 11. ?interrupts and programmable mult i-level interrupt cont roller? on page 108 . the enabled interrupt will trigger according to the intmode setting. ? bit 3 - hsmode: analog comparator high-speed mode select setting this bit selects high-speed mode and clearing this bit to select low-power mode. ? bits 2:1 - hysmode[1:0]: analog comparator hysteresis mode select these bits select hysteresis according to table 25-2 . for details on actual hysteresis levels refer to device data sheet. ? bit 0 - enable: analog comparator enable settings this bit enables the analog comparator n. 25.9.2 acnmuxctrl ? analog comparator control register ? bits 7:6 - res: reserved these bits are unus ed and reserved for future use. for compatibility with futu re devices, always write these bits to zero when this register is written. ? bits 5:3 - muxpos[2:0]: analog comparator positive input mux selection these bits select which input to be connected to the positive input of analog comparator n, according to table 25-3 . table 25-2. analog comparator n hysteresis settings hysmode[1:0] group configuration description 00 no no hysteresis 01 small small hysteresis 10 large large hysteresis 11 - reserved bit 7 6 543210 +0x02 / +0x03 - - muxpos[2:0] muxneg[2:0] acnmuxctrl read/write r r r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 25-3. analog comparator n positive input mux selection muxpos[2:0] group configuration description 000 pin0 pin 0 001 pin1 pin 1 010 pin2 pin 2 011 pin3 pin 3 100 pin4 pin 4
307 8077b?avr?06/08 xmega a ? bits 2:0 - muxneg[2:0]: analog comparator negative input mux selection these bits select which input to be connect ed to the negative input of analog comparator n, according to table 25-4 on page 307 . 25.9.3 ctrla ? cont rol register a ? bits 7:1 - res: reserved these bits are unus ed and reserved for future use. for compatibility with futu re devices, always write these bits to zero when this register is written. ? bit 0 ? ac0out: analog comparator output setting this bit makes the output of analog comparator 0 available on pin 7 on the same port. 25.9.4 ctrlb ? cont rol register b ? bits 7:6 - res - reserved these bits are unus ed and reserved for future use. for compatibility with futu re devices, always write these bits to zero when this register is written. 101 pin5 pin 5 110 pin6 pin 6 111 dac dac output table 25-4. analog comparator n negative input mux selection muxneg[2:0] group configuratio n negative input mux selection 000 pin0 pin 0 001 pin1 pin 1 010 pin3 pin 3 011 pin5 pin 5 100 pin7 pin 7 101 dac dac output 110 bandgap internal bandgap voltage 111 scaler vcc voltage scaler table 25-3. analog comparator n positive input mux selection (continued) bit 76543210 +0x04 -------ac0outctrla read/writerrrrrrrr/w initial value 0 0 0 0 0 0 0 0 bit 76543210 +0x05 - - scalefac[5:0] ctrlb read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000
308 8077b?avr?06/08 xmega a ? bits 5:0 - scalefac[5:0]: analog comparator input voltage scaling factor these bits define the scali ng factor for the vcc voltage f . the input to the analog comparator, v scale , is: 25.9.5 winctrl ? analog comparator window function control register ? bits 7:5 - res: reserved these bits are unus ed and reserved for future use. for compatibility with futu re devices, always write these bits to zero when this register is written. ? bit 4 - wen: analog comparator window enable setting this bit enables window mode for the two analog comparators on the same port. ? bits 3:2 - wintmode[1:0]: analog comparator window interrupt mode settings these bits configure the interrupt mode for analog comparator window mode according to table 25-5 . ? bits 1:0 - wintlvl[1:0]: analog comparator window interrupt enable these bits enable the analog comparator window mode interrupt and select the interrupt level as described in section 11. ?interrupts and programmable multi-level interrupt controller? on page 108 . the enabled interrupt will trigger ac cording to the wintmode setting. 25.9.6 status ? analog comparator common status register ? bits 7:6 - wstate[1:0]: analog comparator window mode current state these bits show the current state of the signal if the window mode is enabled according to table 25-6 . v scale v cc scalefac 1 + () ? 64 ------------------------------------------------------------ - = bit 76543210 +0x06 - - - wen wintmode[1:0] wintlvl[1:0] winctrl read/write r r r r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 25-5. analog comparator window mode interrupt settings wintmode[1:0] group configuration description 00 above interrupt on signal above window 01 inside interrupt on signal inside window 10 below interrupt on signal below window 11 outside interrupt on signal outside window bit 76543210 +0x07 wstate[1:0] ac1state ac0state - wif ac1if ac0if status read/write r/w r/w r/w r/w r r/w r/w r/w initial value 0 0 0 0 0 0 0 0
309 8077b?avr?06/08 xmega a ? bit 5 - ac1state: analog comparator 1 current state this bit shows the current state of the input signal to analog comparator 1. ? bit 4 - ac0state: analog comparator 0 current state this bit shows the current state of the input signal to analog comparator 0. ? bit 3 - res: reserved this bit is unused and reserved fo r future use. for comp atibility with future devices, always write this bit to zero when this register is written. ? bit 2 - wif: analog comparator window interrupt flag this bit holds the interrupt flag for the window mode. wif is set according to the wintmode setting in the section 25.9.5 ?winctrl ? analog comparator window function control regis- ter? on page 308 . ? bit 1 - ac1if: analog comparator 1 interrupt flag this bit holds the interrupt flag for analog comparator 1. ac1if is set according to the int- mode setting in the corresponding section 25.9.1 ?acnctrl ? analog comparator n control register? on page 305 . ? bit 0 - ac0if: analog comparator 0 interrupt flag this bit holds the interrupt flag for analog comparator 0. ac0if is set according to the int- mode setting in the corresponding section 25.9.1 ?acnctrl ? analog comparator n control register? on page 305 . table 25-6. analog comparator window mode current state wstate[1:0] group configuration description 00 above signal is above window 01 inside signal is inside window 10 below signal is below window 11 - reserved
310 8077b?avr?06/08 xmega a 25.10 register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page +0x00 ac0ctrl intmode[1:0] intlvl[1 :0] hsmode hysmode[1:0] enable 305 +0x01 ac1ctrl intmode[1:0] intlvl[1 :0] hsmode hysmode[1:0] enable 305 +0x02 ac0muxctr - - muxpos[2:0] muxneg[2:0] 306 +0x03 ac1muxctr - - muxpos[2:0] muxneg[2:0] 306 +0x04 ctrla - - - - - - - acoout 307 +0x05 ctrlb - - scalefac5:0] 307 +0x06 winctrl - - - wen wintmode[1:0] wintlvl[1:0] 308 +0x07 status wstate[1:0] ac1state ac0state - wif ac1if ac0if 308
311 8077b?avr?06/08 xmega a 26. ieee 1149.1 jtag bo undary scan interface 26.1 features ? jtag (ieee std. 1149.1-2001 compliant) interface. ? boundary-scan capabili ties according to the jtag standard. ? full scan of all i/o pins. ? supports the mandatory sample, preloa d, extest, and bypass instructions. ? supports the optional idcode, highz, and clamp instructions. ? supports the avr specific pdicom instruct ion for accessing the pdi for debugging and programming in its optional jtag mode. 26.2 overview the jtag boundary-scan interface is mainly intended for testing pcbs by using the jtag boundary-scan capability. secondary, the jtag interface is reused to access the program and debug interface (pdi) in its optional jtag mode. the boundary-scan chain has the c apability of driving and observing the logic levels on i/o pins. at system level, all ics having jtag capabilities are connected serially by the tdi/tdo signals to form a long shift register. an external controller sets up the devices to drive values at their out- put pins, and observe the input values received from other devices. the controller compares the received data with the expected result. in this way, boundary-scan provides a mechanism for testing interconnections and integrity of components on printed circuit boards by using the four tap signals only. the ieee 1149.1-2001 defined mandatory jtag instructions idcode, bypass, sample/ preload, and extest together with the option al clamp, and highz instructions can be used for testing the print ed circuit board. initial scanning of the data register path will show the id-code of the device, since id code is the default jtag instruction. if needed, the bypass instruction can be issued to make the shorte st possible scan chain through the device. the extest instruction is used for sampling external pins and loading output pins with data. the data from the output latch will be driven out on t he pins as soon as the extest instruction is loaded into the jtag ir-register. therefore to avoid damaging the board when issuing the extest instruction for the first time, the merg ed sample/preload should be used for setting initial values to the scan ring. sample/preload is also used for taking a non-intrusive snap- shot of the external pins during normal operation of the part. the clamp instruction allows static pin values to be applied via the boundary-scan registers while bypassing these registers in the scan path, efficiently shortening the total length of the serial test path. alternatively the highz instruction can be used to place all i/o pins in an inactive drive state, while bypassing the boundary-scan register chain of the chip. the avr specific pdicom instruction makes it possible to use the pdi data register as an inter- face for accessing the pdi for programming and debugging. note that the pdicom instruction has nothing to do with boundary-scan testing, but represents an alternative way to access inter- nal programming and debugging resources by using the jtag interface. for more details on pdi, programming and on-chip debug refer to section 27. ?program and debug interface? on page 318 . the jtagen fuse must be programmed and the jtagd bit in the mcucr register must be cleared to enable the jtag interface and test access port.
312 8077b?avr?06/08 xmega a when using the jtag interface for boundary- scan, the jtag tck clock frequency can be higher than the internal device frequency. the sy stem clock in the device is not required for boundary-scan. 26.3 tap - test access port the jtag interface is accessed through four of the avr's pins. in jtag terminology, these pins constitute the test access port - tap. these pins are: ? tms: test mode select. this pin is used for navigating through the tap-controller state machine. ? tck: test clock. jtag operation is synchronous to tck. ? tdi: test data in. serial input data to be shifted in to the instruction register or data register (scan chains). ? tdo: test data out. serial output data from instruction register or data register. the ieee std. 1149.1-2001 also sp ecifies an optional tap signal ; trst - test reset. this is not available. when the jtagen fuse is unprogrammed or the jtag disable bit is set the jtag interface is disabled. the four tap pins are normal port pins and the tap controller is in reset. when enabled, the input tap signals are internally pu lled high and the jtag is enabled for boundary- scan operations. figure 26-1. tap controller state diagram
313 8077b?avr?06/08 xmega a the tap controller is a 16-state finite state machine that controls the operation of the boundary- scan circuitry. the state transitions depicted in figure 26-1 depend on the signal present on tms (shown adjacent to each state transition) at the time of the rising edge at tck. the initial state after a power-on reset is test-logic-reset. assuming run-test/idle is the present state, a typical scenario for using the jtag interface is: ? at the tms input, apply the sequence 1, 1, 0, 0 at the rising edges of tck to enter the shift instruction register - shift-ir state. while in this state, shift the four bits of the jtag instructions into the jtag instruction register from the tdi input at the rising edge of tck. the tms input must be held low during input of the 3 lsbs in order to remain in the shift-ir state. the msb of the instruction is shifted in when this state is left by setting tms high. while the instruction is shifted in from the tdi pin, the captured ir-state 0x01 is shifted out on the tdo pin. the jtag instruction selects a particular data register as path between tdi and tdo and controls the circuitry surrounding the selected data register. ? apply the tms sequence 1, 1, 0 to re-enter the run-test/idle state. the instruction is latched onto the parallel output from the shift register path in the update-ir state. the exit-ir, pause-ir, and exit2-ir states are only used for navigating the state machine. ? at the tms input, apply the sequence 1, 0, 0 at the rising edges of tck to enter the shift data register - shift-dr state. while in this state, upload the selected data register (selected by the present jtag instruction in the jtag instruction register) from the tdi input at the rising edge of tck. in order to remain in the shift-dr state, the tms input must be held low during input of all bits except the msb. the msb of the data is shifted in when this state is left by setting tms high . while the data register is sh ifted in from the tdi pin, the parallel inputs to the data register captured in the capture-dr state is shifted out on the tdo pin. ? apply the tms sequence 1, 1, 0 to re-enter the run-test/idle state. if the selected data register has a latched parallel-output, the latching takes place in the update-dr state. the exit-dr, pause-dr, and exit2-dr states are only used for navigating the state machine. as shown in the state diagram, the run-test/idle state need not be entered between selecting jtag instruction and using data registers. note: independent of the initial state of the tap controller, the test-logic-reset state can always be entered by holding tms high for five tck clock periods. 26.4 jtag instructions the instruction register is 4-bit wides. listed below are the jtag instructions for boundary- scan operation and the pdicom instruction used for accessing the pdi in jtag mode. the lsb is shifted in and out first for all shift registers. the opcode for each instruction is shown behind the instruction name in hex format. the text describes which data register is selected as path between tdi and tdo for each instruction. 26.4.1 extest; 0x1 extest is mandatary and the instruction for selecting the boundary-scan chain as data regis- ter for testing circuitry external to the avr package. for the i/o port pins, both output control (dir) and output data (out) is controllable via the scan chain, while the output control and actual pin value is observable. the contents of the latched outputs of the boundary-scan chain is driven out as soon as the jtag ir-register is loaded with the extest instruction.
314 8077b?avr?06/08 xmega a the active states are: ? capture-dr: data on the external pins are sampled into the boundary-scan chain. ? shift-dr: data in the boundary-scan chain is shifted by the tck input. ? update-dr: data from the scan chain is applied to output pins. 26.4.2 idcode; 0x3 ideoce is mandatory and the instruction for select ing the 32 bit id-register as data register. the id-register consists of a version number, a device number and the manufacturer code cho- sen by jedec. this is the default instruction after power-up. the active states are: ? capture-dr: data in the idcode register is sampled into the device identification register. ? shift-dr: the idcode scan chain is shifted by the tck input. 26.4.3 sample/preload; 0x2 sample/reload mandatory and the instruction for pre-loading the output latches and taking a snapshot of the input/output pins without affecting system operation. however, the output latches are not connected to the pins. the boundary-scan chain is selected as data register. note that since each of the sample and preload instructions implements the functionality of the other, they share a common binary value, and can be treated as one single merged instruction. the active states are: ? capture-dr: data on the external pins are sampled into the boundary-scan chain. ? shift-dr: the boundary-scan chain is shifted by the tck input. ? update-dr: data from the boundary-scan chain is applied to the output latches. however, the output latches are not connected to the pins. 26.4.4 bypass; 0xf bypass is mandatory and th e instruction for selecting the bypa ss register for data register. the active states are: ? capture-dr: loads a logic "0" into the bypass register. ? shift-dr: the bypass register cell between tdi and tdo is shifted. 26.4.5 clamp; 0x4 clamp is optional and the instruction for allowing the state of the input/output pins to be deter- mined from the preloaded output latches. the by pass register is selected as data register. the active states are: ? capture-dr: loads a logical "0" into the bypass register. ? shift-dr: the bypass register cell between tdi and tdo is shifted. 26.4.6 highz; 0x5 highz is optional and the instruction for putting all outputs in an inactive drive state (e.g. high impedance). the bypass register is selected as data register. the active states are:
315 8077b?avr?06/08 xmega a ? capture-dr: loads a logical "0" into the bypass register. ? shift-dr: the bypass register cell between tdi and tdo is shifted. 26.4.7 pdicom; 0x7 pdico is an avr specific instruction and usin g the jtag tap as an alternative interface towards the pdi (programming and debug interface). the active states are: ? capture-dr: parallel data from the pdi is sampled into the pdicom data register. ? shift-dr: the pdicom data register is shifted by the tck input. ? update-dr: commands or operands are parallel-latched from the pdicom data register into the pdi. 26.5 data registers the supported data registers that can be connected between tdi and tdo are: ? bypass register (ref: register a in figure 26-2 on page 315 ). ? device identification register (ref: registers c in figure 26-2 on page 315 ). ? boundary-scan chain (ref: register d in figure 26-2 on page 315 ). ? pdicom data register (ref: register b in figure 26-2 on page 315 ) figure 26-2. jtag data register overview 26.5.1 bypass register the bypass register consists of a single shift register stage. when the bypass register is selected as path between tdi and tdo, the register is reset to 0 when leaving the capture-dr controller state. the bypass register can be used to shorten the scan chain on a system when the other devices are to be tested. d d tdi a b b b c c c c tdo tms d d d d d d d d d i/o po rts pdi jtag tck to all tck registers internal registers jtag boundary-scan chain tap ctrl
316 8077b?avr?06/08 xmega a 26.5.2 device identification register figure 26-3. device identification register 26.5.2.1 version version is a 4-bit number identifying the revision of the component. the jtag version number follows the revision of the device. revision a is 0x0, revision b is 0x1 and so on. 26.5.2.2 part number the part number is a 16-bit code identifying the component. refer to the device data sheets to find the correct number. 26.5.2.3 manufacturer id the manufacturer id is an 11-bit code identifyi ng the manufacturer. for atmel this code is 11x01f. 26.5.3 boundary-scan chain the boundary-scan chain has the capability of driv ing and observing the logic levels on all i/o pins. refer to section 26.6 ?boundary-scan chain? on page 316 for a complete description. 26.5.4 pdicom data register the pdicom data register is a 9-bit wide register used for serial-to-parallel - and parallel-to- serial conversion of data between the jtag tap and the pdi. for details refer to section 27. ?program and debug interface? on page 318 . 26.6 boundary-scan chain the boundary-scan chain has the capability of dr iving and observing the logic levels on the i/o pins. to ensure a predictable chip behavior during and after the instructions extest, clamp and highz, the chip is automatically put in rese t. during active reset, the external oscillators, analog modules, and non-default port settings (like pull-up/down, bus-keeper, wired-and/-or) are disabled. it should be noted that the current chip - and port state is unaffected by the sam- ple and preload instructions. 26.6.1 scanning the port pins figure 26-4 on page 317 shows the boundary-scan cell used for all the bi-directional port pins. this cell is able to control and observe both pin direction and pin value via a two-stage shift register. when no alternate port function is pres ent, output control corresponds to the dir reg- ister value, output data corresponds to the out register value, and input data corresponds to the in register value (tapped before the input inverter and - synchronizer). mode represents either an active clamp or extest instruction, while shiftdr is set when the tap controller is in its shift-dr state. msb lsb bit 31 28 27 12 11 1 0 device id version part number manufacturer id 1 4 bits 16 bits 11 bits 1 bit
317 8077b?avr?06/08 xmega a figure 26-4. bidirectional boundary scan cell 26.6.2 scanning the pdi pins. two observe-only cells are inserted to make the combined reset and pdi_clk pin, and the pdi_data pin observable. even though the pdi_da ta pin is bi-directional, it is only made observable in order to avoid any extra logic on the pdi_data output path. figure 26-5. an observe-only input cell d q d q d q d q input data (in) output data (in) output control (dir) mode pn shift dr to next cell from last cell clock dr update dr 0 1 0 1 0 0 1 1 en d q from last cell clock dr to next cell to system logic from system pin shift dr 1 0
318 8077b?avr?06/08 xmega a 27. program and debug interface 27.1 features ? program and debug interface (pdi) ? 2-pin interface for external programming and on-chip debugging ? uses reset pin and dedicated test pin ? no i/o pins required during programming or debugging ? programming features ? flexible communication protocol ? 8 flexible instructions. ? minimal protocol overhead. ? fast ? 10 mhz programming clock at 1.8v v cc ? reliable ? built in error detection and handling ? debugging features ? non-intrusive operation ? uses no hardware or software resource ? complete program flow control ? symbolic debugging support in hardware ? go, stop, reset, step into, step over, step out, run-to-cursor ? 1 dedicated program address breakpoint or symbolic breakpoint for avr studio/emulator ? 4 hardware breakpoints ? unlimited number of user program breakpoints ? uses cpu for accessing i/o, data, and program ? high speed operation ? no limitation on system clock frequency ? jtag interface ? jtag (ieee std. 1149.1 compliant) interface ? boundary-scan capa bilities according to the ieee std. 1149. 1 (jtag) standard ? programming features as for pdi ? on-chip debug features as for pdi 27.2 overview the program and debug interface (pdi) is an atmel proprietary interface for external program- ming and on-chip debugging of the device. the pdi supports high-speed programming of all non-volatile memory (nvm) spaces; flash, eepom, fuses, lockbits and the user signature row. this is done by access ing the nvm con- troller, and executing nvm controller commands as described in memory programming. the on-chip debug (ocd) system supports fully intrusive operation. during debugging no soft- ware or hardware resources in the device is used (except for four i/o pins required if jtag connection is used). the ocd system has full pr ogram flow control, supports unlimited number of program and data breakpoints and has full access (read/write) to all memories. both programming and debugging can be done through two physical interfaces. the primary interface is the pdi physical. this is a 2-pin interface using the reset pin for the clock input
319 8077b?avr?06/08 xmega a (pdi_clk), and the dedicated test pin for data input and output (pdi_data). a jtag interface is also available on most devices, and this ca n be used for programming and debugging through the 4-pin jtag interface. the jtag interfac e is ieee std. 1149.1 compliant, and supports boundary scan. unless otherwise stated, all references to the pdi assumes access through the pdi physical. any external programmer or on-chip debugger/emulator can be directly connected to these interfaces, and no external components are required. figure 27-1. the pdi with jtag and pdi physical and closely related modules (grey) 27.3 pdi physical the pdi physical layer handles the basic low-level serial communication. the physical layer uses a bi-directional half-duplex synchronous serial receiver and transmitter (as a usart in usrt mode). the physical layer includes start-of-frame detection, frame error detection, parity generation, parity error detec tion, and collision detection. the pdi is accessed through two pins: ? pdi_clk: pdi clock input (reset pin). ? pdi_data: pdi data input/output (test pin). in addition to these two pins, v cc and gnd must also be connected between the external pro- grammer/debugger and the device. figure 27-2 on page 319 shows a typical connection. figure 27-2. pdi connection pdi controller jtag physical (physical layer) pdi physical (physical layer) ocd nvm controller program and debug interface (pdi) pdi_clk pdi_data tdo tck tmi tdi nvm memories internal interfaces pdibus programmer/ debugger pdi_data (test) vcc pdi_clk (reset) gnd
320 8077b?avr?06/08 xmega a the remainder of this section is only intended for third parties developing programming support for xmega. 27.3.1 enabling the pdi physical must be enabled before it can be used. this is done by first forcing the pdi_data line high for a period longer than t he equivalent external reset minimum pulse width. this will disable the reset functionality of the reset pin, if not already disabled by the fuse set- tings. the reset pin function can be used as normal until disabled. in the next step of the enabling procedure the pdi_data line must be k ept high for 16 pdi_clk cycles (16 positive edges detected). after this the pdi is enabled and ready to receive instructions. the enable sequence is shown in figure 27-3 on page 320 . figure 27-3. sequence for enabling the pdi. 27.3.2 disabling if the clock frequency on the pdi_clk is lower than approximately 10 khz, this is regarding as inactivity on the clock line. this will then automatically disable the pdi. if not disabled by fuse, the reset function on the reset (pdi_clk) pin is automatically enabled again. if the time-out occurs during the pdi enabling sequence, the whole sequence must be started from the beginning. this also means that the minimum programming frequency is approximately 10 khz. 27.3.3 frame format and characters the pdi physical layer uses a fixed frame format. a serial frame is defined to be one character of eight data bits with start and stop bits and a parity bit. figure 27-4. pdi serial frame format. disable reset function on reset (pdi_clk) pin activate pdi pdi_data pdi_clk table 1. st start bit, always low. (0-7) data bits (0 to 7) p parity bit, even parity is used sp1 stop bit 1, always high. sp2 stop bit 2, always high. st 012 3 4567p sp1 frame sp2 (idle) (st/idle)
321 8077b?avr?06/08 xmega a 27.3.3.1 characters three different characters, data, break and idle, are used. the break character is equal to 12 bit-length of low level. the idle character is equal to 12 bit-length of high level. both the break and the idle character can be extended beyond the bit-length of 12. figure 27-5. characters and timing for the pdi physical. 27.3.4 serial transmission and reception the pdi physical layer is either in transmit (tx) or receive (rx) mode of operation. by default it is in rx mode, waiting for a start bit. the programmer and the pdi operate synchronously on the pdi_clk provided by the program- mer. the dependency between the clock edges and data sampling or data change is fixed. as illustrated in figure 27-6 on page 321 , output data (either from the programmer or from the pdi) is always set up (changed) on t he falling edge of pdi_clk, while data is always sampled on the rising edge of pdi_clk. figure 27-6. changing and sampling of data. 27.3.5 serial transmission when a data transmission is initiated (by the pdi controller), the transmitter simply shifts the start bit, data bits, the parity bit, and the two stop bits out on the pdi_data line. the transmis- sion speed is dictated by the pdi_clk signal. wh ile in transmission mode, idle bits (high bits) are automatically transmi tted to fill possible gaps between successive data characters. if a col- lision is detected during transmission, the output dr iver is disabled and the interface is put into a rx mode waiting for a break character. start 012 3 4567p stop 1 idle character break idle 1 data character 1 break character pdi_clk pdi_data sample sample sample
322 8077b?avr?06/08 xmega a 27.3.5.1 drive contention and collision detection in order to reduce the effect of a drive contention (the pdi and the programmer drives the pdi_data line at the same time ), a mechanism for collision dete ction is supported. the mecha- nism is based on the way the pdi drives data out on the pdi_data line. as shown in figure 7, the output pin driver is only active when the output value changes (from 0-1 or 1-0). hence, if two or more successive bit values are the same, the value is only actively driven the first clock cycle. after this point the output driver is auto matically tri-stated, and the pdi_data pin has a bus-keeper responsible for keeping the pin-valu e unchanged until the output driver is re-enabled due to a bit value change. figure 27-7. driving data out on the pdi_data using bus-keeper if the programmer and the pdi both drives the pdi_data line at the same time, the situation of drive contention will oc cur as illustrated in figure 27-8 on page 322 . every time a bit value is kept for two or more clock cycles, the pdi is able to verify that the correct bit value is driven on the pdi_data line. if the programmer is drivin g the pdi_data line to the opposite bit value than what the pdi expects, a collision is detected. figure 27-8. drive contention and collision de tection on the pdi_data line as long as the pdi transmits al ternating ones and zeros, collisi ons cannot be detected because the output driver will be active all the time pr eventing polling of the pdi_data line. however, within a single frame the two stop bits shoul d always be transmitted as ones, enabling collision detection at least once per frame. 10110 output enable pdi_clk driven output 0 1 pdi_data pdi_clk pdi output pdi_data 10x1 1 programmer output x1 collision detect = collision
323 8077b?avr?06/08 xmega a 27.3.6 serial reception when a start bit is detected, the receiver starts to collect the eight data bits and shift them into the shift register. if the parity bit does not correspond to the parity of the data bits, a parity error has occurred. if one or both of the stop bits are low, a frame error has occurred. if the parity bit is correct, and no frame error detected, the received data bits are parallelized and made available for the pdi controller. 27.3.6.1 break detector when the pdi is in tx-mode, a break character signalized by the programmer will not be inter- preted as a break, but cause a generic data collis ion. when the pdi is in rx-mode, a break character will be recognized as a break. by transmitting two succes sive break characters (must be separated by one or more high bits), the la st break character will always be recog- nized as a break, regardless of whether the pdi was in tx- or rx-mode initially. 27.3.7 direction change in order to ensure correct timing of the half-duplex operation, a simple guard time mechanism is added to the pdi physical interface during direction change. when the pdi changes from operating in rx-mode to operate in tx-mode, a configurable number of additional idle bits are inserted before the start bit is transmitted. t he minimum transition time between rx- and tx- mode is two idle cycles, and these are always inserted. writing the guard time bits in the pdi controller?s control register specifies the additional guard time. the default guard time value is +128 bits. figure 27-9. pdi direction change by inserting idle bits the programmer will loose control of the pdi_data line at the point where the pdi target changes from rx- to tx-mode. the guard time relaxes this critical phase of the communica- tion. when the programmer changes from rx-mo de to tx-mode, minimum a single idle bit should be inserted before the start bit is transmitted. 27.4 jtag physical the jtag physical layer handles the basic low-le vel serial communication over four i/o lines; tms, tck, tdi, and tdo. the jtag physical layer includes break detection, parity error detection, and parity generation. for more details refer to ?ieee 1149.1 jtag boundary scan interface? on page 311 . 27.4.1 enabling the jtagen fuse must be programmed and the jtag disable bit in the mcu control register must be cleared to enable the jtag interface. by default the jtagen fuse is programmed, and the jtag interface is enabled. when the jtag instruction pdicom is shifted into the jtag instruction register, the pdi communication register is chosen as the data register connected st p sp1 1 data character sp2 idle bits st v 1 data character sp1 sp2 dir. change d2w data receive (rx) d2w data transmit (tx) data from d2w interface to emulator data from emulator to d2w interface guard time # idle bits inserted
324 8077b?avr?06/08 xmega a between tdi and tdo. in this mode, the jtag interface can be used to access the pdi for external programming and on-chip debug. 27.4.2 disabling the jtag interface can be disabled by either unprogramming the jtagen fuse or by setting the jtag disable bit in the mcu control register from the application code 27.4.3 jtag instruction set the xmega jtag instruction set consist of eight instructions related to boundary scan and pdi access for nvm programming, for details on the instruction set refer to ?jtag instructions? on page 313 . 27.4.3.1 the pdicom instruction the 9-bit pdi communication register is selected as data register. commands are shifted into the register, while results from previous commands are shifted out from the register. the active tap-controller states are: ? capture-dr: parallel data from the pdi controller is sampled into the pdi communication register. ? shift-dr: the pdi communication register is shifted by the tck input. ? update-dr: commands or operands are parallel-latched into registers in the pdi controller. 27.4.4 frame format and characters the jtag physical layer supports a fixed frame format. a serial frame is defined to be one char- acter of eight data bits followed by one parity bit. figure 27-10. jtag serial frame format 27.4.4.1 special data characters three data characters are given a special meaning. common for all three characters is that the parity bit is inverted in order to force par ity error upon recepti on. the break character (0xbb+p1) is used by the external programmer to force the pdi to abort any on-going operation and bring the pdi controller into a known stat e. the delay character (0xdb+p1) is used by the pdi to tell the programmer that it has no data ready programmer that it has no transmission pending (i.e. the pdi is in rx-mode). table 1. (0-7) data/command bits, least significant bit sent first (0 to 7) p parity bit, even parity is used 012 3 4567 p frame
325 8077b?avr?06/08 xmega a figure 27-11. special data characters 27.4.5 serial transmission and reception the jtag interface supports full duplex communication. at the same time as input data is shifted in on the tdi pin, output data is shifted out on the tdo pin. however, pdi communica- tion relies on half duplex data transfer. dictated by the pdi controller, the jtag physical layer operates in either transmit- (tx) or receive- (rx) mode. the available jtag bit channel is used for control and status signalling. the programmer and the jtag interface operate synchronously on the tck clock provided by the programmer. the dependency between the clock edges and data sampling or data change is fixed. as illustrated in figure 27-10 on page 324 , tdi and tdo is always set up (changed) on the falling edge of tck, while data always should be sampled on the rising edge of tck. figure 27-12. changing and sampling data 27.4.6 serial transmission when data transmission is initiated, a data byte is loaded in parallel into the shift register, and then serialized by shifting the byte out on tdo. the parity bit is generated and stitched to the data byte during transmission. the transmissi on speed is dictated by the tck signal. 27.4.6.1 status signalling if the pdi is in tx-mode (as a response to an ld-instruction), and a transmission request from the pdi controller is pending when the tap-controller enters the capture-dr state, valid data will be parallel-loaded into the shift-register and a correct pa rity bit will be ge nerated an d trans- mitted along with the data byte in the shift-dr state. if the pdi is in rx-mode when the tap-controller enters the capture-dr state, an empty byte (0xeb) will be parallel-loaded into the shift-register, and the parity bit will be set (forcing a parity p1 110 1 1101 1 break character (bb+p1) 1 delay character (db+p1) 1 empty character (eb+p1) p1 110 1 1011 p1 110 1 0111 tck tdi/tdo sample sample sample
326 8077b?avr?06/08 xmega a error) when data is shifted out in the shift-dr state. this situation occurs during normal pdi command - and operand reception. if the pdi is in tx-mode (as a response to an ld-instruction), but no transmission request from the pdi controller is yet pending when the tap-controller enters the capture-dr state, a delay byte (0xdb) will be parallel- loaded into the shift-register, and the parity bit will be set (forcing a parity error) when data is shifted out in the shift-dr state. this situation occurs during data transmission if the data to be transmitted is not yet available. figure 27-13 on page 326 shows an uninterrupted flow of data frames from the pdi (device) as a response to the repeated indirect ld instruction. however, in this example the device is not able to return data bytes faster than one valid byte per two transmitted frames, intermediate delay characters are inserted. figure 27-13. date not ready marking if a delay data frame is transmitted as a response to an ld instruction, the programmer should interpret this as if the jtag-interface had no da ta yet ready for transmission in the previous dr- capture state. the proper reaction from the programmer is to initiate repeated transfers until a valid data byte is received. the ld-instruction is defined to return a specified number of valid frames, not just a number of frames. hence if the programmer detects a delay character after transmitting an ld-instruction, the ld-instructi on should not be retransmitted, because the first ld response would still be pending. 27.4.7 serial reception during reception, the receiver collects the eight data bits and the parity bit from tdi and shifts them into the shift register. every time a valid frame is received, the data is latched in a parallel way in the update-dr state. 27.4.7.1 parity checker the parity checker calculates the parity (even mode) of the data bits in incoming frames and compares the result with the parity bit from the serial frame. in case of a parity error, the pdi controller is signalized. 27.4.7.2 break detector the parity checker is active in both tx- and rx-m ode. if a parity error is detected, the received data byte is evaluated and co mpared with the break character (which a lways will generate a parity error). in case the br eak character is recognized, t he pdi controller is signalized. rep cnt ld *(ptr) external programmer device 0xdb 1 d0 p 0xdb 1 d1 p frame 0 frame 1 frame 2 frame 3 frame 0 frame 1 frame 2 commands/data
327 8077b?avr?06/08 xmega a 27.5 pdi controller the pdi controller includes data transmission/reception on a byte level, command decoding, high-level direction control, control and status register access, exception handling, and clock switching (pdi_clk or tck). the interaction bet ween a programmer and the pdi controller is based on a scheme where the programmer transmits various types of requests to the pdi con- troller, which in tu rn responds in a way according to the specific request. a programmer request comes in the form of an instruction, which may be followed by one or more byte operands. the pdi controller response may be silent (e.g. a data byte is stored to a location within the target), or it may involve data to be returned back to the programmer (e.g. a data byte is read from a location within the target). 27.5.1 switching between pdi- and jtag-mode the pdi controller uses either the jtag - or the pdi physical layer for establishing a connection to the programmer. based on this, the pdi is said to be in either jtag or pdi mode. when one of the modes are entered, the pdi controller regi sters will be initialized, and the correct clock source is selected by the clo ck system. it should be noted that the pdi mode has higher priority than the jtag mode. hence, if the pdi mode is enabled while the pdi controller is already in jtag mode, the access layer will au tomatically switch over to pdi mode. still, if by some reason a user wants to switch physical layer without pow er on/off the device, the active layer should be disabled (to trigger a reset of the pdi) befo re the alternative physical layer is enabled. 27.5.2 accessing internal interfaces after an external programmer has established communication with the pdi, the internal inter- faces are not accessible by default. to get access to the nvm controller and the nvm memories for programming, a un ique key must be signalized by using the key instruction. the internal interfaces is accessed as one linear address space using a dedicated bus (pdibus) between the pdi and the internal interfaces. 27.5.3 nvm programming key the key that must be sent using the key instruction is 128 bits long. the key that will enable nvm programming is: 0x1289ab45cdd888ff 27.5.4 exception handling there are several situations that are consider ed exceptions from normal operation. the excep- tions depends on whether the pdi is in rx - or tx mode, and whether pdi or jtag mode is used. while the pdi is in rx mode, these exceptions are defined as: ?pdi: ? the physical layer detects a parity error. ? the physical layer detects a frame error. ? the physical layer recognizes a break charac ter (also dete cted as a frame error). ?jtag: ? the physical layer detects a parity error. ? the physical layer recognizes a break charac ter (also detected as a parity error).
328 8077b?avr?06/08 xmega a while the pdi is in tx mode, these exceptions are defined: ?pdi: ? the physical layer det ects a data collision. ?jtag: ? the physical layer detects a parity error (on the dummy data shifted in on tdi). ? the physical layer recognizes a break character. all exceptions signalized to the pdi controller. all on-going operations are then aborted and the pdi is put in the error state. the pdi will remain in this state until a break is sent from the external programmer, and th is will bring the pdi back to its default rx state. a consequence of this mechanism is that the programmer can always synchronize the protocol by transmitting two successive break characters. 27.5.5 reset signalling through the reset register, the programmer can issue a reset and force the device into reset. after clearing the reset register, reset is released unless some other reset source is active. 27.5.6 instruction set the pdi has a small instructions set that is used fo r all access to the pdi itself and to the internal interfaces.all instructions are byte instructions. most of the instructions require a number of byte operands following the instruction. the instructions allow to external programmer to access the pdi controller, the nvm cont roller and the nvm memories. 27.5.6.1 lds - load data from pdibus data space using direct addressing the lds instruction is used to load data from the pdibus data space for serial read-out. the lds instruction is based on direct addressing, which means that the address must be given as an argument to the instruction. even though the protocol is based on byte-wise communication, the lds instruction supports multiple-bytes address - and data access. four different address/data sizes are supported; byte, word, 3 bytes, and long (4 bytes). it should be noted that multiple-bytes access is intern ally broken down to repeated single-byte accesses. the main advantage with the multiple-bytes access is that it gives a way to reduce the protocol overhead. when using the lds, the address byte(s) must be transmitted before the data transfer. 27.5.6.2 sts - store data to pdibus data space using direct addressing the st instruction is used to store data that is se rially shifted into the ph ysical layer shift-register to locations within the pdibus data space. the sts instruction is based on direct addressing, which means that the address must be given as an argument to the instruction. even though the protocol is based on byte-wise communication, the st instruction supports multiple-bytes address - and data access. four different address/data sizes are supported; byte, word, 3 bytes, and long (4 bytes). it should be noted that mult iple-bytes access is internally broken down to repeated single-byte accesses. the main advant age with the multiple-bytes access is that it gives a way to reduce the protocol overhead. when using the sts, the address byte(s) must be transmitted before the data transfer.
329 8077b?avr?06/08 xmega a 27.5.6.3 ld - load data from pdibus data space using indirect addressing the ld instruction is used to load data from the pdibus data space to the physical layer shift- register for serial read-out. the ld instruction is based on indirect addres sing (pointer access), which means that the address must be stored into the pointer register prior to the data access. indirect addressing can be combined with pointer increment. in addition to read data from the pdibus data space, the pointer register can be read by the ld instruction. even though the protocol is based on byte-wise communication, the ld instruction supports multiple-bytes address - and data access. four different address/data sizes are supported; byte, word, 3 bytes, and long (4 bytes). it should be noted that mult iple-bytes access is internally broken down to repeated single-byte accesses. the main advant age with the multiple-bytes access is that it gives a way to reduce the protocol overhead. 27.5.6.4 st - store data to pdibus data space using indirect addressing the st instruction is used to store data that is se rially shifted into the ph ysical layer shift-register to locations within the pdibus data space. the st instruction is based on indirect addressing (pointer access), which means that the address must be stored into the pointer register prior to the data access. indirect addressing can be combined with pointer increment. in addition to write data to the pdibus data space, the pointer register can be written by the st instruction. even though the protocol is based on byte-wise communication, the st instruction supports multiple- bytes address - and data access. four different address/data sizes are supported; byte, word, 3 bytes, and long (4 bytes). it should be noted that multiple-bytes access is internally broken down to repeated single-byte accesses. the main advantage with the multiple-bytes access is that it gives a way to reduce the protocol overhead. 27.5.6.5 ldcs - load data from pdi control and status register space the ldcs instruction is used to load data from the pdi control and status registers to the physical layer shift-register for serial read-out. the ldcs instruction supports only direct addressing and single-byte access. 27.5.6.6 stcs - store data to pdi control and status register space the stcs instruction is used to store data that is serially shifted into th e physical layer shift-reg- ister to locations within the pdi control and st atus registers. the stcs instruction supports only direct addressing and single-byte access. 27.5.6.7 key - set activation key the key instruction is used to communicate the activation key bytes that is required for activat- ing the nvm interfaces. 27.5.6.8 repeat - set instruction repeat counter the repeat instruction is used to store count val ues that are serially shifted into the physical layer shift-register to the repeat counter regist er. the instruction that is loaded directly after the repeat instruction operand(s) will be re peated a number of times according to the speci- fied repeat counter register value. hence, the initial repeat counter value plus one, gives the total number of times the instruction will be executed. setting the repeat counter register to zero makes the following instruction run once without being repeated. the repeat cannot be repea ted. the key instruction cannot be repeated, and will override the current value of the repeat counter register
330 8077b?avr?06/08 xmega a 27.5.7 instruction set summary the pdi instruction set summary is shown in figure 27-14 on page 330 . figure 27-14. pdi instruction set summary 0 0 lds 0 size a size b cmd 0 1 0 sts 1 0 0 ldcs cs address 1 1 0 stcs 1 1 0 0 0 key 1 1 0 0 0 0 repeat 1 size b lds sts st 0 1 0 0 0 1 1 1 ld 0 0 0 0 cmd ldcs (lds control/status) stcs (sts control/status) key 1 0 0 1 1 1 repeat 1 1 1 1 0 0 size b - data size byte 3 bytes long (4 bytes) 0 1 0 0 0 1 1 1 word (2 bytes) cs address (cs - control/status reg.) 0 0 0 register 0 register 2 reserved register 1 0 0 0 0 0 0 0 0 1 0 0 0 1 reserved 1 1 1 1 ...... 0 0 size a - address size (direct access) byte 3 bytes long (4 bytes) 0 1 0 0 0 1 1 1 word (2 bytes) 0 0 ld 1 ptr size a/b cmd 0 1 1 st 0 0 0 0 ptr - pointer access (indirect access) *(ptr) ptr ptr++ - reserved 0 1 0 0 0 1 1 1 *(ptr++) 0 0
331 8077b?avr?06/08 xmega a 27.6 register description - pdi instruction and ad dressing registers these registers are all internal registers that are involved in instruction decoding or pdibus addressing. none of these registers are ac cessible as register in a register space. 27.6.1 instruction register when an instruction is successfully shifted into the physical layer shift-register, it is copied into the instruction register. the instruction is retained until another instruction is loaded. the rea- son for this is that the repeat command may force the same instruction to be run repeatedly requiring command decoding to be performed several times on the same instruction. 27.6.2 pointer register the pointer register is used to store an address value specifying locations within the pdibus address space. during direct data access, the pointer register is updated by the specified num- ber of address bytes given as operand bytes to the instruction. during indirect data access, addressing is based on an address already stored in the pointer register prior to the access itself. indirect data access can be optionally combined with pointer register post-increment. the indirect access mode has an option that makes it possible to load or read the pointer register without accessing any other registers. any register update is performed in a little-endian fashion. hence, loading a single byte of the address register will always update the lsb byte while the msb bytes are left unchanged. the pointer register is not involved in addressing registers in the pdi control and status regis- ter space (csrs space). 27.6.3 repeat counter register the repeat instruction will alwa ys be accompanied by one or more operand bytes that define the number of times the next instruction should be repeated. these operand bytes are copied into the repeat counter register upon reception. during the repeated executions of the instruc- tion following immediatel y after the repeat instruction and its operands, t he repeat counter register is decremented until it reaches zero, indi cating that all repetitions are completed. the repeat counter is also involved in key reception. 27.6.4 operand count register immediately after and instruction (except the ldcs and the stcs instructions) a specified num- ber of operands or data bytes (given by the size parts of the instruction) are expected. the operand count register is used to keep track of how many bytes that have been transferred. 27.7 register descrip tion - pdi control and status register these register are registers that are accessible in the pdi control and status register space (csrs) using the instructions ldcs and stcs. the csrs is allocated for registers directly involved in configuration and status monitoring of the pdi itself.
332 8077b?avr?06/08 xmega a 27.7.1 status - program and debug interface status register ? bit 7:2 - res: reserved bits these bits are reserved and will always be read as zero. for compatibility with future devices, always write these bits to zero when this register is written. ? bit 1- nvmen: non-volatile memory enable this status bit is set when the key signalling enables the nvm programming interface. the external programmer can poll this bit to verify successful enabling. writing the nvmen bit dis- ables the nvm interface ? bit 0 - res: reserved bit this bit is reserved and will a lways be read as zero. for compat ibility with future devices, always write this bit to zero when this register is written. 27.7.2 reset - program and debug interface reset register ? bit 7:0 - reset[7:0]: reset signature when the reset signature - 0x59 - is written to reset, the device is forced into reset. the device is kept in reset until reset is written with a data value different from the reset signature (0x00 is recommended). reading the least lsb bit the will return the status of the reset. the 7 msb bits will always return the va lue 0x00 regardless of whether th e device is in reset or not. 27.7.3 ctrl - program and debug interface control register ? bit 7:3 - res: reserved these bits are unus ed and reserved for future use. for compatibility with futu re devices, always write these bits to zero when this register is written. ? bit 2:0 - guardtime[2:0]: guard time these bits specify the number of additional idle bi ts of guard time that are inserted in between pdi reception and - transmission direction change. the default guard time is 128 idle bits, bit 76543210 +0x00 ------nvmen-status read/write rrrrrrrr initial value 0 0 0 0 0 0 0 0 bit 76543210 +0x01 reset[7:0] ctrlb read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 +0x02 - - - - - guardtime[2:0] ctrl read/write r r r r r r/w r/w r/w initial value 0 0 0 0 0 0 0 0
333 8077b?avr?06/08 xmega a and the available settings is shown in table 27-1 on page 333 . in order to speed up the commu- nication, the guard time should be set to the lo west safe configuration accepted. it should be noted that no guard time is inserted when switching from tx - to rx mode. table 27-1. guard time settings. guardtime number of idle bits 000 +128 001 +64 010 +32 011 +16 100 +8 101 +4 110 +2 111 +0
334 8077b?avr?06/08 xmega a 27.8 register summary address name address name bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page +0x00 status - - - - - - nvmen - 332 +0x01 reset reset[7:] 332 +0x02 ctrl - - - - - guardtime[2:0] 332 +0x03 reserved +0x04 reserved +0x05 reserved +0x06 reserved +0x07 reserved +0x08 reserved +0x09 reserved +0x0a reserved +0x0b reserved +0x0c reserved +0x0d reserved +0x0e reserved +0x0f reserved +0x10 reserved
335 8077b?avr?06/08 xmega a 28. memory programming 28.1 features ? read and write access to all memory spaces from ? external programmers ? application software ? self-programming and boot loader support ? real read-while-write self-programming ? the cpu can run and execute code while flash is being programmed ? any communication interface can be used for program upload/download ? external programming ? support for in-system and production programming ? programming through serial pdi or jtag interface ? fast and reliable interfaces. ? high security with separate boot lock bits for ? external programming access ? boot loader section access ? application section access ? application table access ? reset fuse to select reset vector address to the start of the ? application section, or ? boot loader section ? code efficient algorithm ? efficient read-modify-write support 28.2 overview this section describes how to program the non volatile memory (nvm) in xmega, and covers both self-programming and external programmi ng. the nvm consist of the flash program mem- ory, user signature and calibration rows, fuses and lock bits, and eeprom data memory. for details on the actual memories, how they are or ganized and the register description for the nvm controller used to access the memories, refer to ?memories? on page 18 . the nvm can be accessed for read and write both from application software through self-pro- gramming and from an external programmer. for both external programming and self- programming access to the nvm is done through the common nvm controller, and the two methods of programming are very similar. memory access is done by loading address and/or data into the nvm, and a set of commands and triggers that make the nvm controller perform specific tasks on the nvm. from external programming all memory spaces can be read and written, expect for the calibra- tion row which can only be read. the device can be programmed in-system and is accessed through the pdi using the pdi or jtag physical interfaces, ?external programming? on page 351 describes pdi and jtag in detail. self-programming and boot loader support allows application software in the device to read and write the flash, user si gnature row and eeprom, wr ite the lock bits to a more secure setting, and read the calibration row and fuses. the flash allows read-while-write self-programming meaning that the cpu can continue to operate and execute code while the flash is being pro- grammed. ?self-programming and boot loader support? on page 340 describes this in detail.
336 8077b?avr?06/08 xmega a for both self-programming and external programmi ng it is possible to run an automatic crc check on the flash or a section of the flash to verify its content. the device can be locked to prevent read and/or write of the nvm. there are separate lock bits for external programming access, and self-programming access to the boot loader section, application section and application table section. 28.3 nvm controller all access to the non volatile memories is done through the nvm controller. this controls all nvm timing and access privileges, and hold the status of the nvm. this is the common nvm interface for both the external programming and self-programming. for more details on the nvm controller refer to ?register description - nvm controller? on page 24 . 28.4 nvm commands the nvm controller has a set of commands that decide the task to perform on the nvm. this is issued to the nvm controller by writing the selected command to the nvm command register. in addition data and addresses must be read/written from/to the nvm data and address regis- ters for memory read/write operations. when a selected command is loaded and address and data is setup for the operation, each command has a trigger that will start the operation. bases on the triggers, there are three main types of commands. 28.4.1 action triggered commands action triggered commands are triggered when the command execute (cmdex) bit in the nvm control register a (ctrla) is written. action triggered commands typically are used for opera- tions which do not read or write the nvm such as the crc check. 28.4.2 nvm read triggered commands nvm read triggered commands are triggered when the nvm memory is read, and this is typically used for nvm read operations. 28.4.3 nvm write triggered commands nvm write triggered commands are triggered when the nvn is written, and this is typically used for nvm write operations. 28.4.4 ccp write/execute protection most command triggers are protected from accide ntal modification/execution. this is done using the configuration change protection (ccp) feature which requires a special write or execute sequence in order to change a bit or execute an instruction. for details on the ccp, refer to ?configuration change protection? on page 12 28.5 nvm controller busy when the nvm controller is busy performing an operation, the busy flag in the nvm status register is set and the following registers are blocked for write access: ? nvm command register ? nvm control a register ? nvm control b register ? nvm address registers
337 8077b?avr?06/08 xmega a ? nvm data registers this ensures that the given command is exec uted and the operation finished before a new can start. the external programmer or application software must ensure that the nvm is not addressed while busy with a programming operation. programming any part of th e nvm will automatically block: ? all programming to other parts of the nvm. ? all loading/erasing of the flash and eeprom page buffers. ? all nvm read from external programmers. ? all nvm read from the application section. during self-programming interrupts must be disabled, or the interrupt vector table should be moved to the boot loader sections as described in ?interrupts and programmable multi-level interrupt controller? on page 108 . 28.6 flash and eeprom page buffers the flash memory is upd ated in a page-by- page fashion. the eeprom can be upda ted both in a byte-by-byte and page-by-page fashion. flash and eeprom page programming is done by first filling the associated page buffer, and then writing the entire page buffer to a selected page in flash or eeprom. the size of the page buffers depend on the flash and eeprom si ze in each device, and details on page size and page number is described in each device data sheet. 28.6.1 flash page buffer the flash page buffer is filled one word at the time, and it must be erased before it can be loaded. if an already l oaded location is written a gain, this will corrupt th e content of that flash page buffer location. flash page buffer locations that are not loaded will have the value 0xffff, and this value will then be programmed into the flash page locations. the flash page buffer is automatically erased after: ? a system reset. ? executing the write flash page command. ? executing the erase and write flash page command. ? executing the signature row write command. ? executing the write lock bit command. 28.6.2 eeprom page buffer the eeprom page buffer is filled one byte at the time and it must be erased before it can be loaded. if an already loaded location is written tw ice, this will corrupt the content of that eeprom page buffer location. eeprom page buffer locations that are loaded will get ta gged by the nvm controller. during a page write or page erase, only ta rget locations will be written or erased. locations that are not target, will not be written or erased, and the corresponding eeprom location will remain unchanged. this means that also before an eeprom page erase, data must be loaded to the selected page buffer location to tag them. if the data in the page buffer is not going to be written afterword, the actual values in the buffer does matter.
338 8077b?avr?06/08 xmega a the eeprom page buffer is automatically erased after: ? a system reset. ? executing the write eeprom page command. ? executing the erase and write eeprom page command. ? executing the write lock bit and write fuse commands 28.7 flash and eeprom programming sequences for flash and eeprom p age programming, filling the page bu ffers and writing the page buffer into flash or eeprom is two separate operations. the sequence of this is the same for both self-programming and external programming. 28.7.1 flash programming sequence before programming a flash page with the data in the flash page buffer, the flash page must be erased. programming an un-e rased flash page will corrupt th e content in the flash page. the flash page buffer can be f illed either before the erase flas h page operatio n or between a erase flash page and a write flash page operation: alternative 1, fill the bu ffer before a split page erase and page write: ? fill the flash page buffer. ? perform a flash page erase. ? perform a flash page write. alternative 2, fill the page buffer before an atom ic page erase and write: ? fill the flash page buffer. ? perform a page erase and write. alternative 3, fill the bu ffer after a page erase: ? perform a flash page erase. ? fill the flash page buffer. ? perform a flash page write. the nvm command set supports both atomic erase and write operations, and split page erase and page write commands. this split commands e nables shorter programming time for each command and the erase operations can be done during non-time-critical programming execu- tion. when using alternative 1 or 2 above for self-programming, the boot loader provides an effective read-modify-write feature, which allows the software to first read the page, do the nec- essary changes, and then write back the modified data. if alternative 3 is used, it is not possible to read the old data while loading, since the page is already erased. the page address must be the same for both page erase and page write operations when using alternative 1 or 3. 28.7.2 eeprom programming sequence before programming an eeprom page with the selected number of data bytes stored in the eeprom page buffer, the selected locations in the eeprom page must be erased. program- ming an un-erased eepr om page will corrupt th e content in the eepr om page. the eeprom page buffer must be loaded before any page erase or page write operations: alternative 1, fill the page buffer be fore a page erase: ? fill the eeprom page buffer with the selected number of bytes.
339 8077b?avr?06/08 xmega a ? perform a eeprom page erase. ? perform a eeprom page write. alternative 2, fill the buffer before a page er ase and write: ? fill the eeprom page buffer with the selected number of bytes. ? perform an eeprom page erase and write. 28.8 protection of nvm to protect the flash and eeprom memories from wr ite and/or read, lock bits can be set to restrict access from external programmers and the application software. refer to ?lockbits - non-volatile memory lock bit register? on page 33 for details on the available lock bit settings and how to use them. 28.9 preventing nvm corruption during periods when the v cc voltage is below the minimum operating voltage for the device, the result from a flash memory read or write can be corrupt as supply voltage is too low for the cpu and the flash to operate properly. 28.9.1 write corruption to ensure that the voltage is correct during a complete write sequence to the flash memory, the bod and the spike detector is automatically enabled by hardware when the write sequence starts. if a bod or spike detector reset occurs, the programming sequence will be aborted immediately. if this happens, the nvm programming should be restarted when the power is suf- ficient again in case the write sequence failed or only partly succeeded. 28.9.2 read corruption the nvm can be read incorrectly if the supply vo ltage is too low so the cpu execute instructions incorrectly. to ensure that this does not happen the bod can be enabled. 28.10 crc functionality it is possible to run an automatic cyclic redundancy check (crc) on the flash program mem- ory. this can be issued from external programming or software to do a crc on the application section, boot loader section or a selected address range of the flash. once the crc is started, the cpu will be halt ed until the crc is done and the checksum is available in the nvm data register. the cr c takes one cpu clock cycle per word that is included in the crc address range. the polynomial that is used for crc is fixed, and this is: x 24 + 4x 3 + 3x +1.
340 8077b?avr?06/08 xmega a 28.11 self-programming an d boot loader support both the eeprom and the flash memory can be read and written from the application software in the device. this is referred to as self-p rogramming. a boot loader (application code located in the boot loader section of the flash) can both read and write the flash program memory, user signature row and eeprom, an d write the lock bits to a mo re secure setti ng. application code in both the application section can read from the flash, user signature row, calibration row and fuses, and read and write the eeprom. 28.11.1 flash programming the boot loader support provides a real read-while-write self-programming mechanism for downloading and uploading program code by the device itself. this feature allows flexible appli- cation software updates controlled by the devi ce using a boot loader application that reside in the boot loader section in the flash. the boot loader can use any available communication interface and associated protocol to read code and write (program) that code into the flash memory, or read out the program memory code. it has the capability to write into the entire flash, including the boot loader section. the boot loader can thus modify itself, and it can also erase itself from the code if the feature is not needed anymore. 28.11.1.1 application and boot loader sections the application and boot loader sections are different when it comes to self-programming. the application section is read-while-write (rww ) while the boot loader section is no read- while-write (nrww). here ?read-while-write? refers to the section being programmed (erased or written), not the section being read during a boot loader software update. whether the cpu can continue to run and execute code or is halted to stop program execution during a boot loader software update is depending on the flash address being programmed: ? when erasing or writing a page located inside the application section (rww), the boot loader section (nrww) can be read during the operation, thus the cpu can run and execute code from the boot loader section (nrww). ? when erasing or writing a page located inside the boot loader section (nrww), the cpu is halted during the entire operation and code cannot execute. the user signature row section is nrww, hence er asing or writing this section has the same properties as for the boot loader section. during an on-going programming, the software must ensure that the application section is not accessed. doing this will halt the program execut ion from the cpu. the user software can not read data located in the application section during a boot loader software operation. table 28-1. summary of rww and nrww functionality section being addressed by z-pointer during the programming? section that can be read during programming cpu halted read-while-write supported application section (rww) boot loader section (nrww) no ye s boot loader section (nrww) none yes no user signature row section (nrww) none yes no
341 8077b?avr?06/08 xmega a figure 28-1. read-while-write vs. no read-while-write 28.11.1.2 addressing the flash the z-pointer is used to hold the flash memory address for read and write access. the z pointer consists of the zl and zh registers in the r egister file, and rampz register for devices with more than 64k bytes for flash memory. for more details on the z-pointer refer to ?the x-, y- and z- registers? on page 10 . since the flash is word accessed and organized in pages, the z-pointer can be treated as hav- ing two sections. the least significant bits address the words within a page, while the most significant bits address the page within the flash. this is shown in figure 28-2 on page 342 . the word address in the page (fword) is held by the bits [wordmsb:1] in the z-pointer. the remaining bits [pagemsb:wordmsb+1] in the z-pointer holds the flash page address (fpage). together fword and fpage holds an absolute address to a word in the flash. for flash read operations (elpm and lmp), one byte is read at the time. for this the least sig- nificant bit (bit 0) in the z-pointer is used to select the low byte or high byte in the word address. if this bit is 0, the low byte is read, an d if this bit is 1 the high byte is read. the size of fword and fpage will depend on the page and flash size in the device, refer to each device data sheet for details on this. once a programming operation is initiated, the address is latched and the z-pointer can be updated and used for other operations. application section - read-while-write (rww) boot loader section - no read-while-write (nrww) z-pointer adresses rww section z-pointer adresses nrww section cpu is halted during the operation code located in nrww section can be read during the operation
342 8077b?avr?06/08 xmega a figure 28-2. flash addressing for self-programming 28.11.2 nvm flash commands the nvm commands that can be used for acce ssing the flash program memory, signature row and calibration row are listed in table 28-1 . for self-programming of the flash, the trigge r for action triggered commands is to set the cmdex bit in the nvm ctrla register (cmd ex). the read triggered commands are trig- gered by executing the (e)lpm instruction (lpm). the write triggered commands is triggered by a executing the spm instruction (spm). the change protected column indicate if the tr igger is protected by the configuration change protection (ccp). this will require a timed sequence to write/execute the trigger, for more details refer to ?ccp - configuration change protection register? on page 13 . the two last col- umns shows the address pointer used for addressing, and the source/destination data register. section 28.11.1.1 on page 340 through section 28.11.2.14 on page 346 explains in detail the algorithm for each nvm operation. fpage fword 0/1 bit z-pointer pagemsb wordmsb 0 1 instruction word page page program memory word address within a page page address within the flash fword 00 01 02 pageend 00 01 02 flashend fpage low/high byte select for (e)lpm
343 8077b?avr?06/08 xmega a notes: 1. the flash range crc command used byte addressing of the flash. 2. will depend on the flash section (application or boot loader) that is actually addressed. 3. this command is qualified with the lock bits, and requires that the boot lock bits are unprogrammed. 28.11.2.1 read flash the (e)lpm instruction is used to read one byte from the flash memory. 1. load the z-pointer with the byte address to read. 2. load the nvm command register (nvm cmd) with the no operation command. 3. execute the lpm instruction. the destination register will be loaded durin g the execution of the lpm instruction. table 28-2. flash self-programming commands cmd[6:0] group configuration description trigger cpu halted nvm busy change protected address pointer data register 0x00 no_operation no operation / read flash -/(e)lpm -/n n -/n -/ z-pointer -/rd flash page buffer 0x23 load_flash_buffer load flash page buffer spm n n n z-pointer r1:r0 0x26 erase_flash_buffer erase flash page buffer cmdex n y y z-pointer - flash 0x2b erase_flash_page erase flash page spm n/y (2) yyz-pointer - 0x02e write_flash_page write flash page spm n/y (2) yyz-pointer - 0x2f erase_write_flash_page erase & write flash page spm n/y (2) yyz-pointer - 0x3a flash_range_crc (3) flash range crc cmdex y y y data/addr (1) data application section 0x20 erase_app erase application section spm y y y z-pointer - 0x22 erase_app_page erase application section page spm n y y z-pointer - 0x24 write_app_page write application section page spm n y y z-pointer - 0x25 erase_write_app_page erase & write application section page spm n y y z-pointer - 0x38 app_crc application section crc cmdex y y y - data boot loader section 0x2a erase_boot_page erase boot loader section page spm y y y z-pointer - 0x2c write_boot_page write boot loader section page spm y y y z-pointer - 0x2d erase_write_boot_page erase & write boot loader section page spm y y y z-pointer - 0x39 boot_crc boot loader section crc cmdex y y y - data user signature row 0x03 read_user_sig_row read user signature row lpm n n n z-pointer rd 0x18 erase_user_sig_row erase user signature row spm y y y - - 0x1a write_user_sig_row write user signature row spm y y y - - calibration row 0x02 read_calib_row read calibration row lpm n n n z-pointer rd
344 8077b?avr?06/08 xmega a 28.11.2.2 erase flash page buffer the erase flash page buffer command is used to erase the flash page buffer. 1. load the nvm cmd with the erase flash page buffer command. 2. set the command execute bit (nvmex) in the nvm control register a (nvm ctrla) by using the timed ccp sequence. the nvm busy (busy) flag in the nvm status register (nvm status) will be set until the page buffer is erased. 28.11.2.3 load flash page buffer the load flash page buffer command is used to load one word of data into the flash page buffer. 1. load the nvm cmd register with the load flash page buffer command. 2. load the z-pointer with the word address to write. 3. load the data word to be written into the r1:r0 registers. 4. execute the spm instruction. the spm instruction is not protected when performing a flash page buffer load. repeat step 2-4 until th e complete flash page bu ffer is loaded. unloaded locations will have the value 0xffff, and this is not a valid avr cpu opcode/instruction. 28.11.2.4 erase flash page the erase flash page command is used to erase one page in the flash. 1. load the z-pointer with the flash page address to erase. the page address must be written to pcpage. other bits in the z-po inter will be ignored du ring this operation. 2. load the nvm cmd register with the erase flash page command. 3. execute the spm instruction using the timed ccp sequence. the busy flag in the nvm status register will be set until the erase oper ation is finished. the flash section busy (fbusy) flag is set as long the flash is busy, and the application section cannot be accessed. 28.11.2.5 write flash page the write flash page command is used to write the flash page buffer into one flash page in the flash. 1. load the z-pointer with the flash page to write. the page address must be written to pcpage. other bits in the z-pointer will be ignored during this operation. 2. load the nvm cmd register with the write flash page command. 3. execute the protected spm instruction by using the timed ccp sequence. the busy flag in the nvm status register will be set until the wr ite operation is finished. the fbusy flag is set as long the flash is busy, and the application section cannot be accessed. 28.11.2.6 flash range crc the flash range crc command can be used to verify the content in an address range in flash after a self-programming. 1. load the nvm cmd register with the flash range crc command. 2. load the start byte address in the nvm address register (nvm addr). 3. load the end byte address in nvm data register (nvm data).
345 8077b?avr?06/08 xmega a 4. set the cmdex bit in the nvm ctrla register by using the timed ccp sequence. the busy flag in the nvm status register will be set, and the cpu is ha lted during the execu- tion of the command. the crc checksum will be availabl e in the nvm data register. in order to use the flash range crc all the bo ot lock bits must be unprogrammed (no locks). the command execution will be aborted if the boot lock bits for an accessed lo cation are set. 28.11.2.7 erase application section the erase application command is used to erase the complete application section. 1. load the z-pointer to point anywhere in the application section. 2. load the nvm cmd register with the erase application section command 3. execute the spm instruction by using the timed ccp sequence. the busy flag in the status register will be set until the operation is fi nished. the cpu will be halted during the complete execution of the command. 28.11.2.8 erase application section / boot loader section page the erase application section page erase and erase boot loader section page commands are used to erase one page in the application section or boot loader section. 1. load the z-pointer with the flash page address to erase. the page address must be written to zpage. other bits in the z-pointer will be igno red during th is operation. 2. load the nvm cmd register with the erase application/boot section page command. 3. execute the spm instruction by using the timed ccp sequence. the busy flag in the nvm status register will be set until the erase oper ation is finished. the fbusy flag is set as long the flash is busy, and the application section cannot be accessed. 28.11.2.9 application section / boot loader section page write the write application section page and write boot loader section page commands are used to write the flash page buffer into one flash page in the application section or boot loader section. 1. load the z-pointer with the flash page to write. the page address must be written to pcpage. other bits in the z-pointer will be ignored during this operation. 2. load the nvm cmd register with the write application section/boot loader section page command. 3. execute the spm instruction by using the timed ccp sequence. the busy flag in the nvm status register will be set until the wr ite operation is finished. the fbusy flag is set as long the flash is busy, and the application section cannot be accessed. an invalid page address in the z-pointer will abort the nvm command. the erase application section page command requires that the z-pointer addresses the application section, and the erase boot section page command requires that the z-pointer addresses the boot loader section. 28.11.2.10 erase & write application section / boot loader section page the erase & write application section page and erase & write boot loader section page com- mands are used to erase one flash page and then writ e the flash page buffer into that flash page in the application section or boot loader section, in one atomic operation.
346 8077b?avr?06/08 xmega a 1. load the z-pointer with the flash page to write. the page address must be written to pcpage. other bits in the z-pointer will be ignored during this operation. 2. load the nvm cmd register with the erase & write application section/boot loader section page command. 3. execute the spm instruction by using the timed ccp sequence. the busy flag in the nvm status register wi ll be set until the operation is finished. the fbusy flag is set as long the flash is busy, and the application section cannot be accessed. an invalid page address in th e z-pointer will abort the nvm co mmand. the erase & write appli- cation section command requires that the z-pointer addresses the application section, and the erase & write boot section page command requires that the z-pointer addresses the boot loader section. 28.11.2.11 application section / boot loader section crc the application section crc and boot loader section crc commands can be used to verify the application section and boot loader section content after self-programming. 1. load the nvm cmd register with the ap plication section/ bo ot load section crc command. 2. set the cmdex bit in the nvm ctrla register by using the timed ccp sequence. the busy flag in the nvm status register will be set, and the cpu is ha lted during the execu- tion of the crc command. the crc checksum will be available in the nvm data registers. 28.11.2.12 erase user signature row the erase user signature row command is used to erase the user signature row. 1. load the nvm cmd register with the erase user signature row command. 2. execute the spm instruction by using the timed ccp sequence. the busy flag in the nvm status register will be set, and the cpu will be halted until the erase operation is finished. th e user signature row is nrww. 28.11.2.13 write user signature row the write signature row command is used to wr ite the flash page buffer into the user signa- ture row. 1. set up the nvm cmd register to write user signature row command. 2. execute the spm instruction by using the timed ccp sequence. the busy flag in the nvm status register will be set until the operation is finished, and the cpu will be halted during the write operation. the flash page buffer will be cleared during the command execution after the write operation, but the cpu is not halted during this stage. 28.11.2.14 read user signature row / calibration row the read user signature row and red calibrati on row commands are used to read one byte from the user signature row or calibration row. 1. load the z-pointer with the byte address to read. 2. load the nvm cmd register with the re ad user signature row / calibration row command 3. execute the lpm instruction. the destination register will be loaded durin g the execution of the lpm instruction.
347 8077b?avr?06/08 xmega a 28.11.3 nvm fuse and lock bit commands the nvm flash commands that can be used for accessing the fuses and lock bits are listed in table 28-3 . for self-programming of the fuses and lock bits, the trigger for action triggered commands is to set the cmdex bit in the nvm ctrla register (cmdex). the read triggered commands are triggered by executing the (e)lpm instruction (lpm). the write triggered commands is trig- gered by a executing the spm instruction (spm). the change protected column indicate if the tr igger is protected by the configuration change protection (ccp). the two last columns shows the address pointer used for addressing, and the source/destination data register. section 28.11.3.1 on page 347 through section 28.11.3.2 on page 347 explains in details the algorithm for each nvm operation. 28.11.3.1 write lock bits write the write lock bits command is used to program the boot lock bits to a more secure settings from software. 1. load the nvm data0 register with the new lock bit value. 2. load the nvm cmd register with the write lock bit command. 3. set the cmdex bit in the nvm ctrla register using the timed ccp sequence. the busy flag in the nvm status register will be set until the command is finished. the cpu is halted during the complete execution of the command. this command can be executed from both the boot loader section and the application section. the eeprom and flash page buffer is automati cally erased when the lock bits are written. 28.11.3.2 read fuses the read fuses command is used to read the fuses from software. 1. load the nvm addr registers with the address to the fuse byte to read. 2. load the nvm cmd register with the read fuses command. 3. set the cmdex bit in the nvm ctrla register by using the timed ccp sequence. the result will be available in the nvm data0 register. the cpu is halted during the complete execution of the command. 28.11.4 eeprom programming the eeprom can be read and writte n from application code in any part of the flash. its is both byte and page accessible. this means that eith er one byte or one page can be written to the eeprom at once. one byte is re ad from the eeprom during read. table 28-3. fuse and lock bit commands cmd[6:0] group configuration description trigger cpu halted change protected address pointer data register nvm busy 0x00 no_operation no operation - - - - - - fuses and lock bits 0x07 read_fuses read fuses cmdex n n addr data y 0x08 write_lock_bits write lock bits cmdex n y addr - y
348 8077b?avr?06/08 xmega a 28.11.4.1 addressing the eeprom the eeprom can be access ed through the nvm cont roller (i/o mapped), similar to the flash program memory, or it can be memory mapped into the data memory space to be accessed similar to sram. when accessing the eeprom through the nvm controller, the nvm address (addr) register is used to address the eeprom, while the nvm data (data) register is used to store or load eeprom data. for eeprom page programming the addr register can be treated as having two section. the least significant bits address the bytes within a page, while the most significant bits address the page within the eeprom. this is shown in figure 28-3 on page 348 . the byte address in the page (e2byte) is held by the bits [1:bytemsb ] in the addr register. the remaining bits [pagemsb:bytemsb+1] in the addr register ho lds the eeprom page address (e2page). together e2byte and e2page hold s an absolute address to a byte in the eeprom. the size of e2word and e2page will depend on the page and flash size in the device, refer to the device data sheet for details on this. figure 28-3. i/o mapped eeprom addressing when eeprom memory mapping is enabled, loading a data byte into the eeprom page buffer can be performed through direct or indirect store instructions. only the least significant bits of the eeprom address are used to determine locations within the page buffer, but the complete memory mapped eeprom address is always required to ensure correct address mapping. reading from the eeprom can be d one directly using di rect or indirect lo ad instructions. when a memory mapped eeprom page buffer load operation is performed, the cpu is halted for 3 cycles before the next instruction is executed. when the eeprom is memory mapped, the eeprom page buffer load and eeprom read functionality from the nvm controller is disabled. e2page e2byte bit nvm addr pagemsb bytemsb 0 data byte page page data memory byte address within a page page address within the eeprom e2byte 00 01 02 e2pageend e2page 00 01 02 e2end
349 8077b?avr?06/08 xmega a 28.11.5 nvm eeprom commands the nvm flash commands that can be used fo r accessing the eeprom through the nvm con- troller are listed in table 28-4 . for self-programming of the eeprom the trigger for action trig gered commands is to set the cmdex bit in the nvm ctrla register (cmdex) . the read triggered command is triggered reading the nvm data0 register (data0). the change protected column indicate if the tr igger is protected by the configuration change protection (ccp). the two last columns shows the address pointer used for addressing, and the source/destination data register. section 28.11.5.1 on page 349 through section 28.11.5.7 on page 350 explains in details the algorithm for each eeprom operation. 28.11.5.1 load eeprom page buffer the load eeprom page buffer command is used to load one byte into the eeprom page buffer. 1. load the nvm cmd register with the load eeprom page buffer command 2. load the nvm addr0 register with the address to write. 3. load the nvm data0 register with the data to write. this will trigger the command. repeat 2-3 until for the arbitrary number of bytes to be loaded into the page buffer. 28.11.5.2 erase eeprom page buffer the erase eeprom buffer comm and is used to erase the eeprom page buffer. 1. load the nvm cmd register with the erase eeprom buffer command. 2. set the cmdex bit in the nvm ctrla register by using the timed ccp sequence. the busy flag in the nvm status register w ill be set until the o peration is finished. 28.11.5.3 epprom page erase the erase eeprom erase command is us ed to erase one eeprom page. 1. set up the nvm cmd register to erase eeprom page command. 2. load the nvm address register with the eeprom page to erase. table 28-4. eeprom self-progr amming commands cmd[6:0] group configuration description trigger cpu halted change protected address pointer data register nvm busy 0x00 no_operation no operation - - - - - - eeprom page buffer 0x33 load_eeprom_buffer load eeprom page buffer data0 n y addr data0 n 0x36 erase_eeprom _buffer erase eeprom page buffer cmdex n y - - y eeprom y 0x32 erase_eeprom_page erase eeprom page cmdex n y addr - y 0x34 write_eeprom_page write eeprom page cmdex n y addr - y 0x35 erase_write_eeprom_page erase & write eeprom page cmdex n y addr - y 0x30 erase_eeprom erase eeprom cmdex n y - - y 0x06 read_eeprom read eeprom cmdex n n addr data0 n
350 8077b?avr?06/08 xmega a 3. set the cmdex bit in the nvm ctrla register by using the timed ccp sequence. the busy flag in the nvm status register w ill be set until the o peration is finished. the page erase commands will only erase the locations that correspond with the loaded and tagged locations in the eeprom page buffer. 28.11.5.4 write eeprom page the write eeprom page co mmand is used to write all locati ons that is load ed in the eeprom page buffer into one page in eeprom. only the locations that are loaded and tagged in the eeprom page buffer will be written. 1. load the nvm cmd register with the write eeprom page command. 2. load the nvm addr register with the address for eeprom page to write. 3. set the cmdex bit in nvm ctrla regist er by using the timed ccp sequence. the busy flag in the nvm status register w ill be set until the o peration is finished. 28.11.5.5 erase & write eeprom page the erase & write eeprom page command is used to first erase an eeprom page and write the eeprom page buffer into that page in eeprom, in one atomic operation. 1. load the nvm cmd register with the erase & write eeprom page command. 2. load the nvm addr register with the address for eeprom page to write. 3. set the cmdex bit in nvm ctrla regist er by using the timed ccp sequence. the busy flag in the nvm status register w ill be set until the o peration is finished. 28.11.5.6 erase eeprom the erase eeprom co mmand is used to erase all the loca tions in all eeprom pages that cor- responds the loaded a nd tagged locations in the eeprom page buffer. 1. set up the nvm cmd regist er to erase epprom command. 2. set the cmdex bit in nvm ctrla regist er by using the timed ccp sequence. the busy flag in the nvm status register w ill be set until the o peration is finished. 28.11.5.7 read epprom the read eeprom command is used to read one byte from the eeprom, 1. load the nvm cmd register with the read epprom command. 2. load the nvm addr register with the address to read. 3. set the cmdex bit in nvm ctrla regist er by using the timed ccp sequence. the data byte read will be av ailable in the nvm data0.
351 8077b?avr?06/08 xmega a 28.12 external programming external programming is the method for programming non volatile code and data into the device from an external programmer or debugger. this can be done both in-system (in-system pro- gramming) or in mass production programming. the only restrictions on clock speed and voltage is the maximum and minimum operating conditions for the device. refer to the device data sheet for details on this. for external programming the device is accessed through the pdi and pdi controller, using either the jtag or pdi physical connection. for details on pdi and jtag and how to enable and use the physical interface, refer to ?program and debug interface? on page 318 . the remainder of this section assume s that the correct physical connection to the pdi is enabled. through the pdi, the external programmer access all nvm memories and nvm controller using the pdi bus. doing this all data and program memory spaces are mapped into the linear pdi memory space. figure 28-4 on page 352 shows the pdi memory space and the base address for each memory space in the device.
352 8077b?avr?06/08 xmega a figure 28-4. memory map for pdi accessing the data and program memories. flash_base = ox0800000 epprom_base = 0x08c0000 fuse_base = 0x08f0020 data_base = 0x1000000 appl_base = flash_base boot_base = flash_base + size_appl calibration_base = 0x008e0200 signature_base = 0x008e0400 0x0000000 fuses application section 16 mb boot section 0x0800000 0x08f0020 top=0x1ffffff eeprom 0x08e0200 1 b srow 0x08c0000 0x08c1000 data (mapped io/ram) 16 mb 0x1000000
353 8077b?avr?06/08 xmega a 28.12.1 enabling external programming interface nvm programming from the pdi requires enabling, and this is one the following fashion. 1. load the reset register in the pdi with 0x59 - th e reset signature. 2. load the correct nvm key in the pdi. 3. poll nvmen in the pdi status regist er (pdi status) until nvmen is set. when the nvmen bit in the pdi status register is set the nvm interface is active from the pdi. 28.12.2 nvm programming 28.12.2.1 addressing the nvm when the pdi nvm interface is enabled, all th e memories in the device is memory-mapped in the pdi address space. for the reminder of this section all references to reading and writing data or program memory addresses from pdi, refer to the memory map as shown in figure 28-4 on page 352 . the pdi is always using byte addressing, hence all memory addresses must be byte addresses. when filling the flash or eeprom page buffers, on ly the least significant bits of the address are used to determine locations within the page buffer. still, the complete memory mapped address for the flash or eeprom page is required to ensure correct address mapping. 28.12.2.2 nvm busy during programming (page erase and page write) when the nvm is busy, the complete nvm is blocked for reading. 28.12.3 nvm commands the nvm commands that can be used for accessing the nvm memories from external program- ming are listed in table 28-5 . this is a super-set of the commands available for self- programming. for external programming, the trigger for action triggered commands is to set the cmdex bit in the nvm ctrla register (cmdex). the read triggered commands are triggered by a direct or indirect load instruction (lds or ld) from the pdi (pdi read). the write triggered com- mands is triggered by a direct or indirect store instruction (sts or st) from the pdi (pdi write). section 28.12.3.1 on page 354 through section 28.12.3.11 on page 357 explains in detail the algorithm for each nvm operation. the commands are protected by the lock bits, and if read and write lock is set, only the chip erase and flash crc commands are available. table 28-5. nvm commands available for external programming cmd[6:0] commands / operation trigger change protected nvm busy 0x00 no operation --- 0x40 chip erase (1) cmdex y y 0x43 read nvm pdi read n n flash page buffer 0x23 load flash page buffer pdi write n n 0x26 erase flash page buffer cmdex y y flash 0x2b erase flash page pdi write n y
354 8077b?avr?06/08 xmega a notes: 1. if the eesave fuse is programmed t he eeprom is preserved during chip erase. 28.12.3.1 chip erase the chip erase command is used to eras e the flash program me mory, eeprom and lock bits. erasing of the eeprom depend eesave fuse setting, refer to ?fusebyte5 - non-vola- tile memory fuse byte 5? on page 32 for details. the user signature row, calibration row and fuses are not effected. 0x02e flash page write pdi write n y 0x2f erase & write flash page pdi write n y 0x78 flash crc cmdex y y application section 0x20 erase application section pdi write n y 0x22 erase application section page pdi write n y 0x24 write application section page pdi write n y 0x25 erase & write application section page pdi write n y 0x38 application section crc cmdex y y boot loader section 0x68 erase boot section pdi write n y 0x2a erase boot loader section page pdi write n y 0x2c write boot loader section page pdi write n y 0x2d erase & write boot loader section page pdi write n y 0x39 boot loader section crc nvmaa y y calibration and user signature sections 0x03 read user signature row pdi read n n 0x18 erase user signature row pdi write n y 0x1a write user signature row pdi write n y 0x02 read calibration row pdi read n n fuses and lock bits 0x07 read fuse pdi read n n 0x4c write fuse pdi write n y 0x08 write lock bits cmdex y y eeprom page buffer 0x33 load eeprom page buffer pdi write n n 0x36 erase eeprom page buffer cmdex y y eeprom 0x30 erase eeprom cmdex y y 0x32 erase eeprom page pdi write n y 0x34 write eeprom page pdi write n y 0x35 erase & write eeprom page pdi write n y 0x06 read eeprom pdi read n n cmd[6:0] commands / operation trigger change protected nvm busy
355 8077b?avr?06/08 xmega a 1. load the nvm cmd register with chip erase command. 2. set the cmdex bit in nvm ctrla register using the timed ccp sequence. once this operation starts the pdibus is dis abled, and the nvmen bit in the pdi status reg- ister is cleared until the operation is finished. poll the nvmen bit until this is set again, indicting the pdibus is enabled. the busy flag in the nvm status register w ill be set until the o peration is finished. 28.12.3.2 read nvm the read nvm command is used to read the flash, eeprom, fu ses, and sig nature and cali- bration row sections. 1. load the nvm cmd register with the read nvm command. 2. read the selected memory address by doing a pdi read operation. dedicated read eeprom, read fuse and read signature ro w and read calibration row commands are also available fo r the various memory sections. the algorithm for these com- mands are the same as for the nvm read command. 28.12.3.3 erase page buffer the erase flash page buffer and erase eeprom page buffer commands are used to erase the flash and eeprom page buffers. 1. load the nvm cmd register with the erase flash/eeprom pa ge buffer command. 2. set the cmdex bit in the nvm ctrla register by using the timed ccp sequence. the busy flag in the nvm status register w ill be set until the o peration is completed. 28.12.3.4 load page buffer the load flash page buffer and load eeprom page buffer commands are used to load one byte of data into the flash and eeprom page buffers. 1. load the nvm cmd register with the load flash/eeprom pa ge buffer command. 2. write the selected memory address by doing a pdi write operation. since the flash page buffer is word accessing and the pdi uses byte addressing, the pdi must write the flash page buffer in correct order. for the write operation, the low-byte of the word location must be written before the high-byte. the low-byte is then written into the temporary register. the pdi then writes the high-byte of the word location, and the low-byte is then written into the word location page bu ffer in the same clock cycle. the pdi interface is automatically halted, before the next pdi instruction can be executed. 28.12.3.5 erase page the erase application section page, erase b oot loader section page, erase user signature row and erase eeprom page commands are used to erase one page in the selected memory space. 1. load the nvm cmd register with erase application section/boot loader section/user signature row/eeprom page command. 2. write the selected page by doing a pdi write. the page is written by addressing any byte location within the page. the busy flag in the nvm status register w ill be set until the o peration is finished.
356 8077b?avr?06/08 xmega a 28.12.3.6 write page the write application section page, write boot loader section page, write user signature row and write eeprom page is used to write a loaded flash/eeprom page buffer into the selected memory space 1. load the nvm cmd register with write application section/boot loader section/user signature row/eeprom page command. 2. write the selected page by doing a pdi write. the page is written by addressing any byte location within the page. the busy flag in the nvm status register w ill be set until the o peration is finished. 28.12.3.7 erase & write page the erase & write application section page, erase & write boot loader section page, and erase & write eeprom page is used to erase one page and then write a loaded flash/eeprom page buffer into that page in the selected memory space, in one atomic operation. 1. load the nvm cmd register with erase & write application section/boot loader sec- tion/user signature ro w/eeprom page command. 2. write the selected page by doing a pdi write. the page is written by addressing any byte location within the page. the busy flag in the nvm status register w ill be set until the o peration is finished. 28.12.3.8 erase application/ boot loader/ eeprom section the erase application section, erase boot loader section and erase eeprom section com- mand is used to erase the complete section selected. 1. load the nvm cmd register with erase application/ boot/ eeprom section command 2. write the selected section by doing a pdi write. the section is written by addressing any byte location within the section. the busy flag in the nvm status register w ill be set until the o peration is finished. 28.12.3.9 application / boot section crc the application section crc and boot loader section crc commands can be used to verify the content of the selected section after programming. 1. load the nvm cmd register with application/ boot loader section crc command 2. set the cmdex bit in the nvm ctrla register by using the timed ccp sequence. the busy flag in the nvm status register will be set until the operation is finished. the crc checksum will be available in the nvm data register. 28.12.3.10 flash crc the flash crc command can be used to verify the content of the flash program memory after programming. the command can be executed independent of the lock bit state. 1. load the nvm cmd register with flash crc command. 2. set the cmdex bit in the nvm ctrla register by using the timed ccp sequence. once this operation starts the pdibus is dis abled, and the nvmen bit in the pdi status reg- ister is cleared until the operation is finished. poll the nvmen bit until this is set again, indicting the pdibus is enabled.
357 8077b?avr?06/08 xmega a the busy flag in the nvm status register will be set until the operation is finished. the crc checksum will be available in the nvm data register. 28.12.3.11 write fuse/ lock bit the write fuse and write lock bit command is used to write the fuses and the lock bits to a more secure setting. 1. load the nvm cmd register with the write fuse/ lock bit command. 2. write the selected fuse or lock bits by doing a pdi write operation. the busy flag in the nvm status register will be set until the command is finished. for lock bit write the lock bit write command can also be used. 28.13 register description refer to ?register description - nv m controller? on page 24 for complete register description on the nvm controller. refer to ?register description - pdi control and status register? on page 331 for complete reg- ister description on the pdi. 28.14 register summary refer to ?register summary? on page 39 for complete register summary on the nvm controller. refer to ?register summary? on page 334 for complete register summary on the pdi.
358 8077b?avr?06/08 xmega a 29. instruction set summary mnemonics operands description operation flags #clocks arithmetic and logic instructions add rd, rr add without carry rd rd + rr z,c,n,v,s,h 1 adc rd, rr add with carry rd rd + rr + c z,c,n,v,s,h 1 adiw rd, k add immediate to word rd rd + 1:rd + k z,c,n,v,s 2 sub rd, rr subtract without carry rd rd - rr z,c,n,v,s,h 1 subi rd, k subtract immediate rd rd - k z,c,n,v,s,h 1 sbc rd, rr subtract with carry rd rd - rr - c z,c,n,v,s,h 1 sbci rd, k subtract immediate with carry rd rd - k - c z,c,n,v,s,h 1 sbiw rd, k subtract immediate from word rd + 1:rd rd + 1:rd - k z,c,n,v,s 2 and rd, rr logical and rd rd ? rr z,n,v,s 1 andi rd, k logical and with immediate rd rd ? k z,n,v,s 1 or rd, rr logical or rd rd v rr z,n,v,s 1 ori rd, k logical or with immediate rd rd v k z,n,v,s 1 eor rd, rr exclusive or rd rd rr z,n,v,s 1 com rd one?s complement rd $ff - rd z,c,n,v,s 1 neg rd two?s complement rd $00 - rd z,c,n,v,s,h 1 sbr rd,k set bit(s) in register rd rd v k z,n,v,s 1 cbr rd,k clear bit(s) in register rd rd ? ($ffh - k) z,n,v,s 1 inc rd increment rd rd + 1 z,n,v,s 1 dec rd decrement rd rd - 1 z,n,v,s 1 tst rd test for zero or minus rd rd ? rd z,n,v,s 1 clr rd clear register rd rd rd z,n,v,s 1 ser rd set register rd $ff none 1 mul rd,rr multiply unsigned r1:r0 rd x rr (uu) z,c 2 muls rd,rr multiply signed r1:r0 rd x rr (ss) z,c 2 mulsu rd,rr multiply signed with unsigned r1:r0 rd x rr (su) z,c 2 fmul rd,rr fractional multiply unsigned r1:r0 rd x rr<<1 (uu) z,c 2 fmuls rd,rr fractional multiply signed r1:r0 rd x rr<<1 (ss) z,c 2 fmulsu rd,rr fractional multiply signed with unsigned r1:r0 rd x rr<<1 (su) z,c 2 des k data encryption if (h = 0) then r15:r0 else if (h = 1) then r15:r0 encrypt(r15:r0, k) decrypt(r15:r0, k) 1/2 branch instructions rjmp k relative jump pc pc + k + 1 none 2 ijmp indirect jump to (z) pc(15:0) pc(21:16) z, 0 none 2 eijmp extended indirect jump to (z) pc(15:0) pc(21:16) z, eind none 2 jmp k jump pc k none 3 rcall k relative call subroutine pc pc + k + 1 none 2 / 3 (1) icall indirect call to (z) pc(15:0) pc(21:16) z, 0 none 2 / 3 (1) eicall extended indirect call to (z) pc(15:0) pc(21:16) z, eind none 3 (1)
359 8077b?avr?06/08 xmega a call k call subroutine pc k none 3 / 4 (1) ret subroutine return pc stack none 4 / 5 (1) reti interrupt return pc stack i 4 / 5 (1) cpse rd,rr compare, skip if equal if (rd = rr) pc pc + 2 or 3 none 1 / 2 / 3 cp rd,rr compare rd - rr z,c,n,v,s,h 1 cpc rd,rr compare with carry rd - rr - c z,c,n,v,s,h 1 cpi rd,k compare with immediate rd - k z,c,n,v,s,h 1 sbrc rr, b skip if bit in register cleared if (rr(b) = 0) pc pc + 2 or 3 none 1 / 2 / 3 sbrs rr, b skip if bit in register set if (rr(b) = 1) pc pc + 2 or 3 none 1 / 2 / 3 sbic a, b skip if bit in i/o register cleared if (i/o(a,b) = 0) pc pc + 2 or 3 none 2 / 3 / 4 sbis a, b skip if bit in i/o register set if (i/o(a,b) =1) pc pc + 2 or 3 none 2 / 3 / 4 brbs s, k branch if status flag set if (sreg(s) = 1) then pc pc + k + 1 none 1 / 2 brbc s, k branch if status flag cleared if (sreg(s) = 0) then pc pc + k + 1 none 1 / 2 breq k branch if equal if (z = 1) then pc pc + k + 1 none 1 / 2 brne k branch if not equal if (z = 0) then pc pc + k + 1 none 1 / 2 brcs k branch if carry set if (c = 1) then pc pc + k + 1 none 1 / 2 brcc k branch if carry cleared if (c = 0) then pc pc + k + 1 none 1 / 2 brsh k branch if same or higher if (c = 0) then pc pc + k + 1 none 1 / 2 brlo k branch if lower if (c = 1) then pc pc + k + 1 none 1 / 2 brmi k branch if minus if (n = 1) then pc pc + k + 1 none 1 / 2 brpl k branch if plus if (n = 0) then pc pc + k + 1 none 1 / 2 brge k branch if greater or equal, signed if (n v= 0) then pc pc + k + 1 none 1 / 2 brlt k branch if less than, signed if (n v= 1) then pc pc + k + 1 none 1 / 2 brhs k branch if half carry flag set if (h = 1) then pc pc + k + 1 none 1 / 2 brhc k branch if half carry flag cleared if (h = 0) then pc pc + k + 1 none 1 / 2 brts k branch if t flag set if (t = 1) then pc pc + k + 1 none 1 / 2 brtc k branch if t flag cleared if (t = 0) then pc pc + k + 1 none 1 / 2 brvs k branch if overflow flag is set if (v = 1) then pc pc + k + 1 none 1 / 2 brvc k branch if overflow flag is cleared if (v = 0) then pc pc + k + 1 none 1 / 2 brie k branch if interrupt enabled if (i = 1) then pc pc + k + 1 none 1 / 2 brid k branch if interrupt disabled if (i = 0) then pc pc + k + 1 none 1 / 2 data transfer instructions mov rd, rr copy register rd rr none 1 movw rd, rr copy register pair rd+1:rd rr+1:rr none 1 ldi rd, k load immediate rd k none 1 lds rd, k load direct from data space rd (k) none 2 (1)(2) ld rd, x load indirect rd (x) none 1 (1)(2) ld rd, x+ load indirect and post-increment rd x (x) x + 1 none 1 (1)(2) ld rd, -x load indirect and pre-decrement x x - 1, rd (x) x - 1 (x) none 2 (1)(2) ld rd, y load indirect rd (y) (y) none 1 (1)(2) ld rd, y+ load indirect and post-increment rd y (y) y + 1 none 1 (1)(2) mnemonics operands description operation flags #clocks
360 8077b?avr?06/08 xmega a ld rd, -y load indirect and pre-decrement y rd y - 1 (y) none 2 (1)(2) ldd rd, y+q load indirect with displacement rd (y + q) none 2 (1)(2) ld rd, z load indirect rd (z) none 1 (1)(2) ld rd, z+ load indirect and post-increment rd z (z), z+1 none 1 (1)(2) ld rd, -z load indirect and pre-decrement z rd z - 1, (z) none 2 (1)(2) ldd rd, z+q load indirect with displacement rd (z + q) none 2 (1)(2) sts k, rr store direct to data space (k) rd none 2 (1) st x, rr store indirect (x) rr none 1 (1) st x+, rr store indirect and post-increment (x) x rr, x + 1 none 1 (1) st -x, rr store indirect and pre-decrement x (x) x - 1, rr none 2 (1) st y, rr store indirect (y) rr none 1 (1) st y+, rr store indirect and post-increment (y) y rr, y + 1 none 1 (1) st -y, rr store indirect and pre-decrement y (y) y - 1, rr none 2 (1) std y+q, rr store indirect with displacement (y + q) rr none 2 (1) st z, rr store indirect (z) rr none 1 (1) st z+, rr store indirect and post-increment (z) z rr z + 1 none 1 (1) st -z, rr store indirect and pre-decrement z z - 1 none 2 (1) std z+q,rr store indirect with displacement (z + q) rr none 2 (1) lpm load program memory r0 (z) none 3 lpm rd, z load program memory rd (z) none 3 lpm rd, z+ load program memory and post-increment rd z (z), z + 1 none 3 elpm extended load program memory r0 (rampz:z) none 3 elpm rd, z extended load program memory rd (rampz:z) none 3 elpm rd, z+ extended load program memory and post- increment rd z (rampz:z), z + 1 none 3 spm store program memory (rampz:z) r1:r0 none - spm z+ store program memory and post-increment by 2 (rampz:z) z r1:r0, z + 2 none - in rd, a in from i/o location rd i/o(a) none 1 out a, rr out to i/o location i/o(a) rr none 1 push rr push register on stack stack rr none 1 (1) pop rd pop register from stack rd stack none 2 (1) bit and bit-test instructions lsl rd logical shift left rd(n+1) rd(0) c rd(n), 0, rd(7) z,c,n,v,h 1 lsr rd logical shift right rd(n) rd(7) c rd(n+1), 0, rd(0) z,c,n,v 1 mnemonics operands description operation flags #clocks
361 8077b?avr?06/08 xmega a notes: 1. cycle times for data memo ry accesses assume internal memo ry accesses, and are not valid for accesses via the external ram interface. 2. one extra cycle must be added when accessing internal sram. rol rd rotate left through carry rd(0) rd(n+1) c c, rd(n), rd(7) z,c,n,v,h 1 ror rd rotate right through carry rd(7) rd(n) c c, rd(n+1), rd(0) z,c,n,v 1 asr rd arithmetic shift right rd(n) rd(n+1), n=0..6 z,c,n,v 1 swap rd swap nibbles rd(3..0) ? rd(7..4) none 1 bset s flag set sreg(s) 1sreg(s)1 bclr s flag clear sreg(s) 0sreg(s)1 sbi a, b set bit in i/o register i/o(a, b) 1 none 1 cbi a, b clear bit in i/o register i/o(a, b) 0 none 1 bst rr, b bit store from register to t t rr(b) t 1 bld rd, b bit load from t to register rd(b) t none 1 sec set carry c 1c1 clc clear carry c 0c1 sen set negative flag n 1n1 cln clear negative flag n 0n1 sez set zero flag z 1z1 clz clear zero flag z 0z1 sei global interrupt enable i 1i1 cli global interrupt disable i 0i1 ses set signed test flag s 1s1 cls clear signed test flag s 0s1 sev set two?s complement overflow v 1v1 clv clear two?s complement overflow v 0v1 set set t in sreg t 1t1 clt clear t in sreg t 0t1 seh set half carry flag in sreg h 1h1 clh clear half carry flag in sreg h 0h1 mcu control instructions break break (see specific descr. for break) none 1 nop no operation none 1 sleep sleep (see specific descr. for sleep) none 1 wdr watchdog reset (see specific descr. for wdr) none 1 mnemonics operands description operation flags #clocks
362 8077b?avr?06/08 xmega a 30. datasheet revision history 30.1 8077b ? 05/08 1. updated ?overview? , ?avr cpu? , ?dmac - direct memory access controller? and ?memories? layout. 2. updated bit names and register names in section 5.14 ?register description ? dma channel? on page 47 . 3. updated bit names and register names in section 4.19 ?register description ? mcu? on page 35 . 4. updated address register in section 4.20.1 ?nvm controller (flash an d eeprom)? on page 39 . 5. updated features in section 6.1 ?features? on page 56 . 6. updated bit name in section 6.8.2 ?chnctrl ? event channel n control register? on page 64 . 7. updated register format in section 21.5 ?register description - aes? on page 239 . 8. updated register format, bit register and register names in section 7. ?system clock and clock options? on page 67 . 9. updated the table layout in table 8-1 on page 87 . 10. updated register description in section 8.6 ?register description ? power reduction registers? on page 89 . 11. updated register description, register names and bit register in section 13. ?tc - 16-bit timer/counter? on page 134 , in section 14. ?awex ? advanced waveform extension? on page 160 and in section 15. ?hi-res - high resolution extension? on page 172 . 12. updated register description, re gister names and bit register in section 12. ?i/o ports? on page 114 , in section 17. ?twi ? two wire interface? on page 180 , in section 16. ?rtc - real time counter? on page 173 , in section 18. ?spi ? serial peripheral interface? on page 204 , in section 19. ?usart? on page 210 , in section 20. ?ircom - ir communication module? on page 231 and in section 23. ?adc - analog to digital converter? on page 264 . 13. updated register description, register names and bit register in section 24. ?dac - digital to analog converter? on page 290 , in section 25. ?ac - analog comparator? on page 302 , in section 26. ?ieee 1149.1 jtag boundary scan interface? on page 311 , and in section 27. ?program and debug interface? on page 318 . 14. removed ?possibility to drive output to ground? from section 24.1 ?features? on page 290 . 15. added ?internal/external reference? in section 24.1 ?features? on page 290 . 16. updated ?bit utilization? in section 24.9.6 ?status ? dac status register? on page 296 . 17. removed parentheses from the section?s title section 24.9.10 ?ch1datal ? dac channel 1 data register low byte? on page 299 . 18. added information text before the table in section 24.10 ?register summary? on page 301 . 19. corrected the vscale formula in section 25.9.4 ?ctrlb ? control register b? on page 307 . 20. merged section 23.3.2 and section 23.3.3 in one section 25.3.2 ?internal inputs? on page 304 . 21. changed ?singed? to signed in section 23.1 ?features? on page 264 . 22. changed awexelock bit from position 4 to position 2 in section 4.19.8 ?awexlock ? advanced waveform extension lock register? on page 38 , and updated the entire section and section 4.20.4 ?mcu registers? on page 40 .
363 8077b?avr?06/08 xmega a 23. added the last paragraph on section 3.8 ?stack and stack pointer? on page 9 . 24. inserted the correct figure 13-1 on page 135 . 25. updated the figure 13-2 on page 137 . 26. updated the figure 12-10 on page 122 . 27. updated the figure 23-15 on page 274 by removing the color. 28. removed section 21.14.6. the removed section was only for the test. 29. updated the table 6-3 on page 62 with a footnote and cross-refe rences to the footnote for porta_pinn to portf_pinn. 30. changed connection description of ctrla in section 25.9.3 ?ctrla ? control register a? on page 307 . ac0out is connected to pin 7, not on pin 0. 31. updated the section 4.1 ?features? on page 18 with ?flexible software crc? in the feature list for the flash. 32. updated figure 7-1 on page 68 . 33. removed figure 26-4 on page 317 and figure 26-5 on page 317 and replaced by ones drawn in visio. 34. updated figure 4-1 on page 19 , figure 4-2 on page 21 and figure 4-3 on page 23 . 35. updated figure 17-11 on page 187 . 36. corrected the bit 0 in section 8.6.1 ?pr - general power reduction register? on page 89 and in section 8.7 ?register summary? on page 92 . 37. updated the text in section 9.4.6 ?software reset? on page 100 . 38. updated the table notes in the table 7-6 on page 80 . 39. updated the figure 6-1 on page 57 with ircom. 40. updated the figure 27-1 on page 319 . 41. changed the initial value to ff on the rtc perh and perl registers in section 16.3.8 ?perh - real time counter period register high? on page 177 and in section 16.3.9 ?perl - real time counter period register l? on page 177 . 42. added a footnote in table 12-5 on page 128 that explains the low level. 43. updated the high byte and low byte in section 4.20.5 ?nvm signature row? on page 40 . 44. inserted a new section 28. ?memory programming? on page 335 . 45. inserted a new figure figure 2-1 on page 4 . 46. inserted a new figure figure 3-1 on page 6 . 47. inserted new sections: ?ebi - external bus interface? on page 243 , ?memory programming? on page 335 , and ?instruction set summary? on page 358 . 48. updated ?virtual registers? on page 123 . 49. deleted 2 chapters: ?bootloader - self-programming? and extern programming. 50. removed ?truegnd? bit from ?register summary? on page 301 .
364 8077b?avr?06/08 xmega a 30.2 8077a ? 02/08 1. initial revision
i 8077b?avr?06/08 xmega a table of contents 1 about this manual ............. ................ ............... .............. .............. ............ 2 1.1 reading the manual ..........................................................................................2 1.2 resources .........................................................................................................2 1.3 recommended reading ....................................................................................2 2 overview ............ ................ ................ ............... .............. .............. ............ 3 2.1 block diagram ...................................................................................................4 2.2 recommended reading .....................................................................................4 3 avr cpu ............... .............. .............. ............... .............. .............. ............ 5 3.1 features ............................................................................................................5 3.2 overview ............................................................................................................5 3.3 architectural overview .......................................................................................5 3.4 alu - arithmetic logic unit ...............................................................................7 3.5 program flow ....................................................................................................7 3.6 instruction execution timing .............................................................................8 3.7 status register ..................................................................................................9 3.8 stack and stack pointer ....................................................................................9 3.9 register file ......................................................................................................9 3.10 ramp and extended indirect registers ..........................................................11 3.11 accessing 16-bits registers ............................................................................12 3.12 configuration change protection ....................................................................12 3.13 fuse lock ........................................................................................................13 3.14 register description ........................................................................................13 3.15 register summary ...........................................................................................17 4 memories ............... .............. .............. ............... .............. .............. .......... 18 4.1 features ..........................................................................................................18 4.2 overview ..........................................................................................................18 4.3 flash program memory ...................................................................................18 4.4 fuses and lockbits ..........................................................................................20 4.5 data memory ...................................................................................................21 4.6 internal sram .................................................................................................21 4.7 eeprom ............... ................ ................ ................ ................ ................ ..........22 4.8 i/o memory ......................................................................................................22 4.9 external memory .............................................................................................22
ii 8077b?avr?06/08 xmega a 4.10 data memory and bus arbitration ...................................................................22 4.11 memory timing ................................................................................................23 4.12 device id .........................................................................................................23 4.13 jtag disable ..................................................................................................23 4.14 io memory protection ......................................................................................24 4.15 register description - nvm controller ............................................................24 4.16 register description ? nvm fuses and lockbits ............................................29 4.17 register description ? general purpose i/o memory .....................................35 4.18 register description ? external memory .........................................................35 4.19 register description ? mcu ............................................................................35 4.20 register summary ...........................................................................................39 5 dmac - direct memory access controller ............... ................. .......... 41 5.1 features ..........................................................................................................41 5.2 overview ..........................................................................................................41 5.3 dma transaction .............................................................................................42 5.4 transfer triggers .............................................................................................42 5.5 addressing .......................................................................................................43 5.6 priority between channels ..............................................................................43 5.7 double buffering ..............................................................................................43 5.8 transfer buffers ...............................................................................................43 5.9 error detection .................................................................................................44 5.10 software reset ................................................................................................44 5.11 protection ........................................................................................................44 5.12 interrupts .........................................................................................................44 5.13 register description ? dma controller ............................................................45 5.14 register description ? dma channel ..............................................................47 5.15 register summary ? dma controller ..............................................................55 5.16 register summary ? dma channel ................................................................55 6 event system ........ .............. .............. ............... .............. .............. .......... 56 6.1 features ..........................................................................................................56 6.2 overview ..........................................................................................................56 6.3 events ..............................................................................................................57 6.4 event routing network ....................................................................................58 6.5 event timing ....................................................................................................60 6.6 filtering ............................................................................................................60
iii 8077b?avr?06/08 xmega a 6.7 quadrature decoder (qdec) ..........................................................................60 6.8 register description ........................................................................................62 6.9 register summary ...........................................................................................66 7 system clock and clock options ................ ................. .............. .......... 67 7.1 features ..........................................................................................................67 7.2 overview ..........................................................................................................67 7.3 clock distribution .............................................................................................68 7.4 clock sources .................................................................................................69 7.5 system clock selection and prescalers ..........................................................71 7.6 pll with 1-31x multiplication factor ................................................................72 7.7 dfll 2 mhz and dfll 32 mhz ......................................................................72 7.8 external clock source failure monitor ............................................................74 7.9 register description - clock ............................................................................75 7.10 register description - oscillator ......................................................................78 7.11 register description - dfll32m/dfll2m ......................................................83 7.12 register summary ...........................................................................................85 8 power management and sleep .... ................ ................. .............. .......... 86 8.1 features ..........................................................................................................86 8.2 overview ..........................................................................................................86 8.3 sleep modes ....................................................................................................86 8.4 power reduction registers .............................................................................88 8.5 register description ? sleep ...........................................................................88 8.6 register description ? power reduction registers .........................................89 8.7 register summary ...........................................................................................92 9 system control and reset ...... ................ ................. ................ ............. 93 9.1 features ..........................................................................................................93 9.2 overview ..........................................................................................................93 9.3 reset sequence ..............................................................................................95 9.4 reset sources .................................................................................................95 9.5 register description ......................................................................................100 9.6 register summary .........................................................................................101 10 wdt ? watchdog timer ......... ................ ................. ................ ............. 102 10.1 features ........................................................................................................102 10.2 overview ........................................................................................................102 10.3 normal mode operation ................................................................................102
iv 8077b?avr?06/08 xmega a 10.4 window mode operation ...............................................................................103 10.5 watchdog timer clock ...................................................................................103 10.6 configuration protection and lock ................................................................103 10.7 registers description ....................................................................................104 10.8 register summary .........................................................................................107 11 interrupts and programmable multi-lev el interrupt cont roller ........ 108 11.1 features ........................................................................................................108 11.2 overview ........................................................................................................108 11.3 operation .......................................................................................................108 11.4 interrupts .......................................................................................................109 11.5 interrupt level .................................................................................................110 11.6 interrupt priority .............................................................................................110 11.7 moving interrupts between application and boot section .............................112 11.8 register description ......................................................................................112 11.9 register summary .........................................................................................113 12 i/o ports ............... .............. .............. .............. .............. .............. ........... 114 12.1 features ........................................................................................................114 12.2 overview ........................................................................................................114 12.3 using the i/o pin ...........................................................................................115 12.4 i/o pin configuration .....................................................................................116 12.5 reading the pin value ...................................................................................118 12.6 input sense configuration .............................................................................119 12.7 port interrupt ..................................................................................................120 12.8 port event ......................................................................................................121 12.9 alternate port functions ................................................................................121 12.10 slew-rate control ...........................................................................................122 12.11 clock and event output .................................................................................122 12.12 multi-configuration .........................................................................................123 12.13 virtual registers ............................................................................................123 12.14 register description ? ports ..........................................................................123 12.15 register description ? multiport configuration ..............................................128 12.16 register description ? virtual port ................................................................131 12.17 register summary ? ports ............................................................................133 12.18 register summary ? port configuration ........................................................133 12.19 register summary ? virtual ports .................................................................133
v 8077b?avr?06/08 xmega a 13 tc - 16-bit timer/counter .. ............. .............. .............. .............. ........... 134 13.1 features ........................................................................................................134 13.2 overview ........................................................................................................134 13.3 block diagram ...............................................................................................136 13.4 clock and event sources ..............................................................................138 13.5 double buffering ............................................................................................138 13.6 counter operation .........................................................................................139 13.7 capture channel ...........................................................................................141 13.8 compare channel .........................................................................................144 13.9 interrupts and events .....................................................................................148 13.10 dma support. ................................................................................................148 13.11 timer/counter commands ............................................................................148 13.12 register description ......................................................................................149 13.13 register summary .........................................................................................159 14 awex ? advanced waveform extension ......... .............. ............ ........ 160 14.1 features ........................................................................................................160 14.2 overview ........................................................................................................160 14.3 port override .................................................................................................161 14.4 dead time insertion ......................................................................................163 14.5 pattern generation ........................................................................................164 14.6 fault protection .............................................................................................165 14.7 register description ......................................................................................166 14.8 register summary .........................................................................................171 15 hi-res - high resolution extension .......... ................ .............. ........... 172 15.1 features ........................................................................................................172 15.2 overview ........................................................................................................172 15.3 register description ......................................................................................172 15.4 register summary .........................................................................................172 16 rtc - real time counter .. .............. .............. .............. .............. ........... 173 16.1 features ........................................................................................................173 16.2 overview ........................................................................................................173 16.3 register description ......................................................................................174 16.4 register summary .........................................................................................179 17 twi ? two wire interface ... .............. ............... .............. .............. ........ 180 17.1 features ........................................................................................................180
vi 8077b?avr?06/08 xmega a 17.2 overview ........................................................................................................180 17.3 general twi bus concepts ...........................................................................181 17.4 twi bus state logic ......................................................................................187 17.5 twi master operation ...................................................................................188 17.6 twi slave operation .....................................................................................190 17.7 enabling external driver interface .................................................................191 17.8 register description - twi control ................................................................192 17.9 register description - twi master ................................................................192 17.10 register description - twi slave ..................................................................198 17.11 register summary - twi ...............................................................................203 17.12 register summary - twi master ...................................................................203 17.13 register summary - twi slave .....................................................................203 18 spi ? serial peripheral interface ......... .............. .............. ............ ........ 204 18.1 features ........................................................................................................204 18.2 overview ........................................................................................................204 18.3 master mode ..................................................................................................205 18.4 slave mode ....................................................................................................205 18.5 data modes ...................................................................................................206 18.6 dma support .................................................................................................207 18.7 register description ......................................................................................207 18.8 register summary .........................................................................................209 19 usart ............. ................. ................ .............. .............. .............. ........... 210 19.1 features ........................................................................................................210 19.2 overview ........................................................................................................210 19.3 clock generation ...........................................................................................212 19.4 frame formats ..............................................................................................215 19.5 usart initialization .......................................................................................216 19.6 data transmission - the usart transmitter ...............................................216 19.7 data reception - the usart receiver ........................................................217 19.8 asynchronous data reception ......................................................................218 19.9 the impact of fractional baud rate generation ...........................................221 19.10 usart in master spi mode ..........................................................................222 19.11 usart spi vs. spi .......................................................................................222 19.12 multi-processor communication mode ..........................................................223 19.13 ircom mode of operation ............................................................................224
vii 8077b?avr?06/08 xmega a 19.14 dma support .................................................................................................224 19.15 register description - usart .......................................................................224 19.16 register summary .........................................................................................230 20 ircom - ir communication module .............. .............. .............. ........ 231 20.1 features ........................................................................................................231 20.2 overview ........................................................................................................231 20.3 registers description - ircom .....................................................................233 20.4 register summary - ircom ..........................................................................234 21 crypto engines ................. .............. .............. .............. .............. ........... 235 21.1 features ........................................................................................................235 21.2 overview ........................................................................................................235 21.3 des instruction ..............................................................................................235 21.4 aes crypto module ........ ................. ................ ............. ............ ............. ........236 21.5 register description - aes ................. ................ ................ ................ ...........239 21.6 register summary - aes ..............................................................................242 22 ebi - external bus interfac e ................ .............. .............. ............ ........ 243 22.1 features ........................................................................................................243 22.2 overview ........................................................................................................243 22.3 chip select ....................................................................................................243 22.4 i/o pin configuration .....................................................................................244 22.5 ebi clock .......................................................................................................245 22.6 sram configuration ......................................................................................245 22.7 sram lpc configuration ..............................................................................247 22.8 sdram configuration ...................................................................................248 22.9 combined sram & sdram configuration ...................................................250 22.10 ebi timing - tbd ...........................................................................................252 22.11 register description - ebi .............................................................................254 22.12 register description - ebi chip select ..........................................................259 22.13 register summary - ebi ................................................................................263 22.14 register summary - ebi chip select ............................................................263 23 adc - analog to digital converter ......... ................. ................ ........... 264 23.1 features ........................................................................................................264 23.2 overview ........................................................................................................264 23.3 input sources .................................................................................................265 23.4 adc channels ...............................................................................................268
viii 8077b?avr?06/08 xmega a 23.5 analog reference ...........................................................................................269 23.6 conversion result .........................................................................................269 23.7 starting a conversion .....................................................................................270 23.8 adc clock and conversion timing ...............................................................270 23.9 dma transfer .................................................................................................274 23.10 interrupts and events .....................................................................................274 23.11 calibration .....................................................................................................274 23.12 channel priority .............................................................................................274 23.13 synchronous sampling ..................................................................................275 23.14 register description - adc ...........................................................................275 23.15 register description - adc channel .............................................................282 23.16 register summary .........................................................................................289 24 dac - digital to analog c onverter .............. .............. .............. ........... 290 24.1 features ........................................................................................................290 24.2 overview ........................................................................................................290 24.3 starting a conversion .....................................................................................291 24.4 output channels ............................................................................................291 24.5 dac clock ......................................................................................................291 24.6 timing constraints .........................................................................................291 24.7 low power mode ...........................................................................................292 24.8 calibration .....................................................................................................292 24.9 register description ......................................................................................292 24.10 register summary .........................................................................................301 25 ac - analog comparator .... .............. ............... .............. .............. ........ 302 25.1 features ........................................................................................................302 25.2 overview ........................................................................................................302 25.3 input channels ..............................................................................................304 25.4 start of signal compare ................................................................................304 25.5 generating interrupts and events ..................................................................304 25.6 window mode ................................................................................................304 25.7 input hysteresis .............................................................................................305 25.8 power consumption vs. propagation delay ....................................................305 25.9 register description ......................................................................................305 25.10 register summary .........................................................................................310 26 ieee 1149.1 jtag b oundary scan interface ........ ................ ............. 311
ix 8077b?avr?06/08 xmega a 26.1 features ........................................................................................................311 26.2 overview ........................................................................................................311 26.3 tap - test access port .................................................................................312 26.4 jtag instructions ..........................................................................................313 26.5 data registers ................................................................................................315 26.6 boundary-scan chain .....................................................................................316 27 program and debug interface ................. ................. ................ ........... 318 27.1 features ........................................................................................................318 27.2 overview ........................................................................................................318 27.3 pdi physical ..................................................................................................319 27.4 jtag physical ...............................................................................................323 27.5 pdi controller ................................................................................................327 27.6 register description - pdi instruction and addressing registers .................331 27.7 register description - pdi control and status register ................................331 27.8 register summary .........................................................................................334 28 memory programming ........ .............. ............... .............. .............. ........ 335 28.1 features ........................................................................................................335 28.2 overview ........................................................................................................335 28.3 nvm controller ..............................................................................................336 28.4 nvm commands ...........................................................................................336 28.5 nvm controller busy .....................................................................................336 28.6 flash and eeprom page buffers ........ ................ ................ ................ ........337 28.7 flash and eeprom programming sequen ces ............ ............ ............. ........338 28.8 protection of nvm .........................................................................................339 28.9 preventing nvm corruption ...........................................................................339 28.10 crc functionality ..........................................................................................339 28.11 self-programming and boot loader support ................................................340 28.12 external programming ...................................................................................351 28.13 register description ......................................................................................357 28.14 register summary .........................................................................................357 29 instruction set summary ... .............. ............... .............. .............. ........ 358 30 datasheet revision history .. ................ ................. ................ ............. 362 30.1 8077b ? 05/08 ...............................................................................................362 30.2 8077a ? 02/08 ...............................................................................................364
x 8077b?avr?06/08 xmega a table of contents.......... ................. ................ ................. ................ ........... i
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